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https://github.com/AsahiLinux/u-boot
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36a9630fcb
Add clk-generic driver compatible with common clock framework. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
202 lines
4.7 KiB
C
202 lines
4.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Generic clock support for AT91 architectures.
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*
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* Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Claudiu Beznea <claudiu.beznea@microchip.com>
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*
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* Based on drivers/clk/at91/clk-generated.c from Linux.
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <linux/io.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/at91_pmc.h>
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#include "pmc.h"
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#define UBOOT_DM_CLK_AT91_GCK "at91-gck-clk"
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#define GENERATED_MAX_DIV 255
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struct clk_gck {
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void __iomem *base;
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const u32 *clk_mux_table;
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const u32 *mux_table;
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const struct clk_pcr_layout *layout;
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struct clk_range range;
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struct clk clk;
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u32 num_parents;
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u32 id;
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};
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#define to_clk_gck(_c) container_of(_c, struct clk_gck, clk)
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static int clk_gck_enable(struct clk *clk)
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{
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struct clk_gck *gck = to_clk_gck(clk);
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pmc_write(gck->base, gck->layout->offset,
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(gck->id & gck->layout->pid_mask));
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pmc_update_bits(gck->base, gck->layout->offset,
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gck->layout->cmd | AT91_PMC_PCR_GCKEN,
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gck->layout->cmd | AT91_PMC_PCR_GCKEN);
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return 0;
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}
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static int clk_gck_disable(struct clk *clk)
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{
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struct clk_gck *gck = to_clk_gck(clk);
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pmc_write(gck->base, gck->layout->offset,
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(gck->id & gck->layout->pid_mask));
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pmc_update_bits(gck->base, gck->layout->offset,
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gck->layout->cmd | AT91_PMC_PCR_GCKEN,
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gck->layout->cmd);
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return 0;
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}
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static int clk_gck_set_parent(struct clk *clk, struct clk *parent)
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{
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struct clk_gck *gck = to_clk_gck(clk);
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int index;
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index = at91_clk_mux_val_to_index(gck->clk_mux_table, gck->num_parents,
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parent->id);
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if (index < 0)
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return index;
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index = at91_clk_mux_index_to_val(gck->mux_table, gck->num_parents,
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index);
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if (index < 0)
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return index;
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pmc_write(gck->base, gck->layout->offset,
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(gck->id & gck->layout->pid_mask));
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pmc_update_bits(gck->base, gck->layout->offset,
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gck->layout->gckcss_mask | gck->layout->cmd,
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(index << (ffs(gck->layout->gckcss_mask) - 1)) |
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gck->layout->cmd);
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return 0;
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}
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static ulong clk_gck_set_rate(struct clk *clk, ulong rate)
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{
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struct clk_gck *gck = to_clk_gck(clk);
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ulong parent_rate = clk_get_parent_rate(clk);
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u32 div;
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if (!rate || !parent_rate)
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return 0;
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if (gck->range.max && rate > gck->range.max)
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return 0;
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div = DIV_ROUND_CLOSEST(parent_rate, rate);
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if (div > GENERATED_MAX_DIV + 1 || !div)
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return 0;
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pmc_write(gck->base, gck->layout->offset,
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(gck->id & gck->layout->pid_mask));
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pmc_update_bits(gck->base, gck->layout->offset,
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AT91_PMC_PCR_GCKDIV_MASK | gck->layout->cmd,
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((div - 1) << (ffs(AT91_PMC_PCR_GCKDIV_MASK) - 1)) |
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gck->layout->cmd);
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return parent_rate / div;
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}
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static ulong clk_gck_get_rate(struct clk *clk)
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{
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struct clk_gck *gck = to_clk_gck(clk);
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ulong parent_rate = clk_get_parent_rate(clk);
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u32 val, div;
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if (!parent_rate)
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return 0;
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pmc_write(gck->base, gck->layout->offset,
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(gck->id & gck->layout->pid_mask));
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pmc_read(gck->base, gck->layout->offset, &val);
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div = (val & AT91_PMC_PCR_GCKDIV_MASK) >>
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(ffs(AT91_PMC_PCR_GCKDIV_MASK) - 1);
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return parent_rate / (div + 1);
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}
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static const struct clk_ops gck_ops = {
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.enable = clk_gck_enable,
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.disable = clk_gck_disable,
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.set_parent = clk_gck_set_parent,
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.set_rate = clk_gck_set_rate,
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.get_rate = clk_gck_get_rate,
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};
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struct clk *
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at91_clk_register_generic(void __iomem *base,
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const struct clk_pcr_layout *layout,
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const char *name, const char * const *parent_names,
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const u32 *clk_mux_table, const u32 *mux_table,
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u8 num_parents, u8 id,
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const struct clk_range *range)
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{
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struct clk_gck *gck;
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struct clk *clk;
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int ret, index;
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u32 val;
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if (!base || !layout || !name || !parent_names || !num_parents ||
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!clk_mux_table || !mux_table || !range)
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return ERR_PTR(-EINVAL);
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gck = kzalloc(sizeof(*gck), GFP_KERNEL);
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if (!gck)
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return ERR_PTR(-ENOMEM);
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gck->id = id;
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gck->base = base;
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gck->range = *range;
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gck->layout = layout;
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gck->clk_mux_table = clk_mux_table;
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gck->mux_table = mux_table;
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gck->num_parents = num_parents;
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clk = &gck->clk;
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clk->flags = CLK_GET_RATE_NOCACHE;
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pmc_write(gck->base, gck->layout->offset,
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(gck->id & gck->layout->pid_mask));
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pmc_read(gck->base, gck->layout->offset, &val);
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val = (val & gck->layout->gckcss_mask) >>
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(ffs(gck->layout->gckcss_mask) - 1);
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index = at91_clk_mux_val_to_index(gck->mux_table, gck->num_parents,
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val);
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if (index < 0) {
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kfree(gck);
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return ERR_PTR(index);
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}
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ret = clk_register(clk, UBOOT_DM_CLK_AT91_GCK, name,
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parent_names[index]);
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if (ret) {
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kfree(gck);
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clk = ERR_PTR(ret);
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}
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return clk;
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}
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U_BOOT_DRIVER(at91_gck_clk) = {
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.name = UBOOT_DM_CLK_AT91_GCK,
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.id = UCLASS_CLK,
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.ops = &gck_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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