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LS2085A is an ARMv8 implementation. This adds board support for emulator and simulator: Two DDR controllers UART2 is used as the console IFC timing is tightened for speedy booting Support DDR3 and DDR4 as separated targets Management Complex (MC) is enabled Support for GIC 500 (based on GICv3 arch) Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
10 lines
233 B
Text
10 lines
233 B
Text
#
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# Copyright 2014 Freescale Semiconductor
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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Freescale LayerScape with Chassis Generation 3
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This architecture supports Freescale ARMv8 SoCs with Chassis generation 3,
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for example LS2085A.
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