mirror of
https://github.com/AsahiLinux/u-boot
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5d6050fdb8
This patch adds the new Barco platinum platform. It currently includes those two boards: platinum-titanium ----------------- This is the same board as the titanium that is already supported in mainline U-Boot. But its now moved to this new platform to support multiple "flavors" of imx6 boards in one directory. Its also moved to support SPL booting. And with this we use the run-time DDR configuration of this SPL support. The board is equipped with the Micron MT41J128M16JT-125 DDR chips. We now can remove the DDR related registers tuples from the imximage.cfg file. As all this is done in the SPL at run-time. platinum-picon -------------- This board is new and based on the MX6DL with 1GiB DDR using the Micron MT41K256M16HA DDR3 chips. Its also equipped with 2 NAND chips (each 512MiB). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Pieter Ronsijn <pieter.ronsijn@barco.com>
244 lines
7 KiB
C
244 lines
7 KiB
C
/*
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* Copyright (C) 2014, Barco (www.barco.com)
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* Copyright (C) 2014 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/imx-common/iomux-v3.h>
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#include <asm/imx-common/mxc_i2c.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include "platinum.h"
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#define GPIO_IP_NCONFIG IMX_GPIO_NR(5, 18)
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#define GPIO_HK_NCONFIG IMX_GPIO_NR(7, 13)
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#define GPIO_LS_NCONFIG IMX_GPIO_NR(5, 19)
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#define GPIO_I2C0_SEL0 IMX_GPIO_NR(5, 2)
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#define GPIO_I2C0_SEL1 IMX_GPIO_NR(1, 11)
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#define GPIO_I2C0_ENBN IMX_GPIO_NR(1, 13)
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#define GPIO_I2C2_SEL0 IMX_GPIO_NR(1, 17)
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#define GPIO_I2C2_SEL1 IMX_GPIO_NR(1, 20)
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#define GPIO_I2C2_ENBN IMX_GPIO_NR(1, 14)
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#define GPIO_USB_RESET IMX_GPIO_NR(1, 5)
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iomux_v3_cfg_t const ecspi1_pads[] = {
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MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI1_PAD_CLK),
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MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO),
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MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI),
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MX6_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS),
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MX6_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(ECSPI_PAD_SS),
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MX6_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(ECSPI_PAD_SS),
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};
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iomux_v3_cfg_t const ecspi2_pads[] = {
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MX6_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(ECSPI2_PAD_CLK),
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MX6_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO),
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MX6_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI),
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MX6_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS),
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MX6_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(ECSPI_PAD_SS),
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};
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iomux_v3_cfg_t const enet_pads[] = {
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MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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};
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/* PHY nRESET */
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iomux_v3_cfg_t const phy_reset_pad = {
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MX6_PAD_SD1_DAT2__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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iomux_v3_cfg_t const uart4_pads[] = {
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MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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iomux_v3_cfg_t const uart5_pads[] = {
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MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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iomux_v3_cfg_t const i2c0_mux_pads[] = {
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MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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iomux_v3_cfg_t const i2c2_mux_pads[] = {
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MX6_PAD_SD1_DAT1__GPIO1_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_SD2_DAT1__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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struct i2c_pads_info i2c_pad_info0 = {
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.scl = {
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.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC_SCL,
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.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC_SCL,
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.gp = IMX_GPIO_NR(5, 27)
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},
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.sda = {
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.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
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.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
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.gp = IMX_GPIO_NR(5, 26)
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}
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};
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struct i2c_pads_info i2c_pad_info2 = {
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.scl = {
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.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC_SCL,
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.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC_SCL,
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.gp = IMX_GPIO_NR(1, 3)
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},
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.sda = {
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.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
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.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
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.gp = IMX_GPIO_NR(1, 6)
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}
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};
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/*
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* This enet related pin-muxing and GPIO handling is done
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* in SPL U-Boot. For early initialization. And to give the
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* PHY some time to come out of reset before the U-Boot
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* ethernet driver tries to access its registers via MDIO.
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*/
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int platinum_setup_enet(void)
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{
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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unsigned phy_reset = IMX_GPIO_NR(1, 19);
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/* First configure PHY reset GPIO pin */
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imx_iomux_v3_setup_pad(phy_reset_pad);
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/* Reconfigure enet muxing while PHY is in reset */
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gpio_direction_output(phy_reset, 0);
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imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
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mdelay(10);
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gpio_set_value(phy_reset, 1);
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udelay(100);
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/* set GPIO_16 as ENET_REF_CLK_OUT */
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setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
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return enable_fec_anatop_clock(ENET_50MHZ);
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}
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int platinum_setup_i2c(void)
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{
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imx_iomux_v3_setup_multiple_pads(i2c0_mux_pads,
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ARRAY_SIZE(i2c0_mux_pads));
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imx_iomux_v3_setup_multiple_pads(i2c2_mux_pads,
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ARRAY_SIZE(i2c2_mux_pads));
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mdelay(10);
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/* Disable i2c mux 0 */
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gpio_direction_output(GPIO_I2C0_SEL0, 0);
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gpio_direction_output(GPIO_I2C0_SEL1, 0);
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gpio_direction_output(GPIO_I2C0_ENBN, 1);
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/* Disable i2c mux 1 */
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gpio_direction_output(GPIO_I2C2_SEL0, 0);
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gpio_direction_output(GPIO_I2C2_SEL1, 0);
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gpio_direction_output(GPIO_I2C2_ENBN, 1);
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udelay(10);
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setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
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setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
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/* Disable all leds */
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i2c_set_bus_num(0);
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i2c_reg_write(0x60, 0x05, 0x55);
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return 0;
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}
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int platinum_setup_spi(void)
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{
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imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
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imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
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return 0;
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}
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int platinum_setup_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
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imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
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return 0;
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}
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int platinum_phy_config(struct phy_device *phydev)
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{
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/* Use generic infrastructure, no specific setup */
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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int platinum_init_gpio(void)
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{
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/* Reset FPGA's */
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gpio_direction_output(GPIO_IP_NCONFIG, 0);
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gpio_direction_output(GPIO_HK_NCONFIG, 0);
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gpio_direction_output(GPIO_LS_NCONFIG, 0);
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udelay(3);
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gpio_set_value(GPIO_IP_NCONFIG, 1);
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gpio_set_value(GPIO_HK_NCONFIG, 1);
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gpio_set_value(GPIO_LS_NCONFIG, 1);
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/* no dmd configuration yet */
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return 0;
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}
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int platinum_init_usb(void)
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{
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/* Reset usb hub */
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gpio_direction_output(GPIO_USB_RESET, 0);
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udelay(100);
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gpio_set_value(GPIO_USB_RESET, 1);
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return 0;
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}
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int platinum_init_finished(void)
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{
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/* Enable led 0 */
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i2c_set_bus_num(0);
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i2c_reg_write(0x60, 0x05, 0x54);
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return 0;
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}
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