Andre Przywara 7656d3982a sunxi: H6: Add DDR3-1333 timings ... Add a routine to program the timing parameters for DDR3-1333 DRAM chips connected to the H6 DRAM controller. The values were gathered from doing back-calculations from a register dump, trying to match them up with the official JEDEC DDDR3 spec. If in doubt, the register dump values were taken for now, but the JEDEC recommendation were added as a comment. Many thanks to Jernej for contributing fixes! Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>		2019-07-16 17:13:04 +05:30
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ddr2_v3s.c	sunxi: add support for the DDR2 in V3s SoC	2017-06-08 22:37:55 +05:30
ddr3_1333.c	sunxi: Add selective DRAM type and timing	2017-06-08 22:37:55 +05:30
h6_ddr3_1333.c	sunxi: H6: Add DDR3-1333 timings	2019-07-16 17:13:04 +05:30
h6_lpddr3.c	sunxi: H6: move LPDDR3 timing definition into separate file	2019-07-16 17:09:31 +05:30
lpddr3_stock.c	sunxi: add LPDDR3 timing from stock boot0	2017-06-08 22:37:55 +05:30
Makefile	sunxi: H6: Add DDR3-1333 timings	2019-07-16 17:13:04 +05:30