mirror of
https://github.com/AsahiLinux/u-boot
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2e4cc1c5d4
Use CPHYSADDR to implement the virt_to_phys function for converting from
a virtual to a physical address for MIPS32, much as is already done for
MIPS64. This allows for virt_to_phys to work regardless of whether the
address being translated is in kseg0 or kseg1, unlike the previous
subtraction based approach which only worked for addresses in kseg0.
This allows for drivers to provide an address to virt_to_phys without
needing to manually ensure that kseg1 addresses are converted to
equivalent kseg0 addresses first.
This patch is equivalent to this Linux patch currently waiting to be
reviewed & merged:
https://patchwork.linux-mips.org/patch/12564/
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
569 lines
16 KiB
C
569 lines
16 KiB
C
/*
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* Copyright (C) 1994, 1995 Waldorf GmbH
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* Copyright (C) 1994 - 2000, 06 Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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* Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
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* Author: Maciej W. Rozycki <macro@mips.com>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _ASM_IO_H
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#define _ASM_IO_H
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#include <linux/bug.h>
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include <asm/addrspace.h>
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#include <asm/byteorder.h>
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#include <asm/cpu-features.h>
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#include <asm/pgtable-bits.h>
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#include <asm/processor.h>
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#include <asm/string.h>
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#include <ioremap.h>
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#include <mangle-port.h>
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#include <spaces.h>
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/*
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* Raw operations are never swapped in software. OTOH values that raw
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* operations are working on may or may not have been swapped by the bus
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* hardware. An example use would be for flash memory that's used for
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* execute in place.
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*/
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# define __raw_ioswabb(a, x) (x)
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# define __raw_ioswabw(a, x) (x)
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# define __raw_ioswabl(a, x) (x)
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# define __raw_ioswabq(a, x) (x)
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# define ____raw_ioswabq(a, x) (x)
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/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
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#define IO_SPACE_LIMIT 0xffff
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#ifdef CONFIG_DYNAMIC_IO_PORT_BASE
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static inline ulong mips_io_port_base(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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return gd->arch.io_port_base;
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}
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static inline void set_io_port_base(unsigned long base)
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{
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DECLARE_GLOBAL_DATA_PTR;
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gd->arch.io_port_base = base;
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barrier();
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}
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#else /* !CONFIG_DYNAMIC_IO_PORT_BASE */
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static inline ulong mips_io_port_base(void)
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{
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return 0;
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}
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static inline void set_io_port_base(unsigned long base)
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{
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BUG_ON(base);
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}
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#endif /* !CONFIG_DYNAMIC_IO_PORT_BASE */
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/*
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* virt_to_phys - map virtual addresses to physical
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* @address: address to remap
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*
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* The returned physical address is the physical (CPU) mapping for
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* the memory address given. It is only valid to use this function on
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* addresses directly mapped or allocated via kmalloc.
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*
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* This function does not give bus mappings for DMA transfers. In
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* almost all conceivable cases a device driver should not be using
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* this function
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*/
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static inline unsigned long virt_to_phys(volatile const void *address)
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{
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unsigned long addr = (unsigned long)address;
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/* this corresponds to kernel implementation of __pa() */
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#ifdef CONFIG_64BIT
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if (addr < CKSEG0)
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return XPHYSADDR(addr);
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#endif
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return CPHYSADDR(addr);
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}
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/*
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* phys_to_virt - map physical address to virtual
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* @address: address to remap
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*
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* The returned virtual address is a current CPU mapping for
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* the memory address given. It is only valid to use this function on
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* addresses that have a kernel mapping
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*
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* This function does not handle bus mappings for DMA transfers. In
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* almost all conceivable cases a device driver should not be using
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* this function
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*/
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static inline void *phys_to_virt(unsigned long address)
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{
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return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
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}
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/*
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* ISA I/O bus memory addresses are 1:1 with the physical address.
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*/
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static inline unsigned long isa_virt_to_bus(volatile void *address)
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{
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return (unsigned long)address - PAGE_OFFSET;
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}
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static inline void *isa_bus_to_virt(unsigned long address)
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{
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return (void *)(address + PAGE_OFFSET);
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}
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#define isa_page_to_bus page_to_phys
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/*
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* However PCI ones are not necessarily 1:1 and therefore these interfaces
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* are forbidden in portable PCI drivers.
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*
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* Allow them for x86 for legacy drivers, though.
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*/
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#define virt_to_bus virt_to_phys
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#define bus_to_virt phys_to_virt
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static inline void __iomem *__ioremap_mode(phys_addr_t offset, unsigned long size,
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unsigned long flags)
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{
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void __iomem *addr;
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phys_addr_t phys_addr;
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addr = plat_ioremap(offset, size, flags);
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if (addr)
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return addr;
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phys_addr = fixup_bigphys_addr(offset, size);
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return (void __iomem *)(unsigned long)CKSEG1ADDR(phys_addr);
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}
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/*
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* ioremap - map bus memory into CPU space
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* @offset: bus address of the memory
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* @size: size of the resource to map
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*
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* ioremap performs a platform specific sequence of operations to
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* make bus memory CPU accessible via the readb/readw/readl/writeb/
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* writew/writel functions and the other mmio helpers. The returned
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* address is not guaranteed to be usable directly as a virtual
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* address.
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*/
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#define ioremap(offset, size) \
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__ioremap_mode((offset), (size), _CACHE_UNCACHED)
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/*
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* ioremap_nocache - map bus memory into CPU space
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* @offset: bus address of the memory
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* @size: size of the resource to map
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*
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* ioremap_nocache performs a platform specific sequence of operations to
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* make bus memory CPU accessible via the readb/readw/readl/writeb/
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* writew/writel functions and the other mmio helpers. The returned
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* address is not guaranteed to be usable directly as a virtual
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* address.
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*
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* This version of ioremap ensures that the memory is marked uncachable
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* on the CPU as well as honouring existing caching rules from things like
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* the PCI bus. Note that there are other caches and buffers on many
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* busses. In particular driver authors should read up on PCI writes
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*
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* It's useful if some control registers are in such an area and
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* write combining or read caching is not desirable:
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*/
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#define ioremap_nocache(offset, size) \
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__ioremap_mode((offset), (size), _CACHE_UNCACHED)
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#define ioremap_uc ioremap_nocache
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/*
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* ioremap_cachable - map bus memory into CPU space
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* @offset: bus address of the memory
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* @size: size of the resource to map
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*
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* ioremap_nocache performs a platform specific sequence of operations to
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* make bus memory CPU accessible via the readb/readw/readl/writeb/
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* writew/writel functions and the other mmio helpers. The returned
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* address is not guaranteed to be usable directly as a virtual
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* address.
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*
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* This version of ioremap ensures that the memory is marked cachable by
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* the CPU. Also enables full write-combining. Useful for some
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* memory-like regions on I/O busses.
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*/
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#define ioremap_cachable(offset, size) \
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__ioremap_mode((offset), (size), _page_cachable_default)
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/*
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* These two are MIPS specific ioremap variant. ioremap_cacheable_cow
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* requests a cachable mapping, ioremap_uncached_accelerated requests a
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* mapping using the uncached accelerated mode which isn't supported on
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* all processors.
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*/
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#define ioremap_cacheable_cow(offset, size) \
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__ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
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#define ioremap_uncached_accelerated(offset, size) \
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__ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
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static inline void iounmap(const volatile void __iomem *addr)
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{
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plat_iounmap(addr);
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}
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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#define war_octeon_io_reorder_wmb() wmb()
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#else
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#define war_octeon_io_reorder_wmb() do { } while (0)
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#endif
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#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
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\
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static inline void pfx##write##bwlq(type val, \
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volatile void __iomem *mem) \
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{ \
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volatile type *__mem; \
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type __val; \
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\
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war_octeon_io_reorder_wmb(); \
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\
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__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
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\
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__val = pfx##ioswab##bwlq(__mem, val); \
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\
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if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
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*__mem = __val; \
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else if (cpu_has_64bits) { \
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type __tmp; \
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\
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__asm__ __volatile__( \
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".set arch=r4000" "\t\t# __writeq""\n\t" \
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"dsll32 %L0, %L0, 0" "\n\t" \
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"dsrl32 %L0, %L0, 0" "\n\t" \
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"dsll32 %M0, %M0, 0" "\n\t" \
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"or %L0, %L0, %M0" "\n\t" \
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"sd %L0, %2" "\n\t" \
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".set mips0" "\n" \
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: "=r" (__tmp) \
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: "0" (__val), "m" (*__mem)); \
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} else \
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BUG(); \
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} \
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\
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static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
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{ \
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volatile type *__mem; \
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type __val; \
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\
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__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
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\
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if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
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__val = *__mem; \
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else if (cpu_has_64bits) { \
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__asm__ __volatile__( \
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".set arch=r4000" "\t\t# __readq" "\n\t" \
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"ld %L0, %1" "\n\t" \
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"dsra32 %M0, %L0, 0" "\n\t" \
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"sll %L0, %L0, 0" "\n\t" \
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".set mips0" "\n" \
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: "=r" (__val) \
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: "m" (*__mem)); \
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} else { \
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__val = 0; \
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BUG(); \
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} \
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\
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return pfx##ioswab##bwlq(__mem, __val); \
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}
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#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p) \
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\
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static inline void pfx##out##bwlq##p(type val, unsigned long port) \
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{ \
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volatile type *__addr; \
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type __val; \
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\
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war_octeon_io_reorder_wmb(); \
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\
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__addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base() + port); \
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\
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__val = pfx##ioswab##bwlq(__addr, val); \
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\
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/* Really, we want this to be atomic */ \
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BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
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\
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*__addr = __val; \
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} \
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\
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static inline type pfx##in##bwlq##p(unsigned long port) \
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{ \
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volatile type *__addr; \
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type __val; \
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\
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__addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base() + port); \
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\
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BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
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\
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__val = *__addr; \
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\
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return pfx##ioswab##bwlq(__addr, __val); \
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}
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#define __BUILD_MEMORY_PFX(bus, bwlq, type) \
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\
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__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
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#define BUILDIO_MEM(bwlq, type) \
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\
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__BUILD_MEMORY_PFX(__raw_, bwlq, type) \
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__BUILD_MEMORY_PFX(, bwlq, type) \
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__BUILD_MEMORY_PFX(__mem_, bwlq, type) \
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BUILDIO_MEM(b, u8)
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BUILDIO_MEM(w, u16)
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BUILDIO_MEM(l, u32)
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BUILDIO_MEM(q, u64)
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#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
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__BUILD_IOPORT_SINGLE(bus, bwlq, type, ) \
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__BUILD_IOPORT_SINGLE(bus, bwlq, type, _p)
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#define BUILDIO_IOPORT(bwlq, type) \
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__BUILD_IOPORT_PFX(, bwlq, type) \
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__BUILD_IOPORT_PFX(__mem_, bwlq, type)
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BUILDIO_IOPORT(b, u8)
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BUILDIO_IOPORT(w, u16)
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BUILDIO_IOPORT(l, u32)
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#ifdef CONFIG_64BIT
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BUILDIO_IOPORT(q, u64)
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#endif
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#define __BUILDIO(bwlq, type) \
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\
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__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
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__BUILDIO(q, u64)
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#define readb_relaxed readb
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#define readw_relaxed readw
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#define readl_relaxed readl
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#define readq_relaxed readq
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#define writeb_relaxed writeb
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#define writew_relaxed writew
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#define writel_relaxed writel
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#define writeq_relaxed writeq
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#define readb_be(addr) \
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__raw_readb((__force unsigned *)(addr))
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#define readw_be(addr) \
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be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
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#define readl_be(addr) \
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be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
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#define readq_be(addr) \
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be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
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#define writeb_be(val, addr) \
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__raw_writeb((val), (__force unsigned *)(addr))
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#define writew_be(val, addr) \
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__raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
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#define writel_be(val, addr) \
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__raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
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#define writeq_be(val, addr) \
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__raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
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/*
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* Some code tests for these symbols
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*/
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#define readq readq
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#define writeq writeq
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#define __BUILD_MEMORY_STRING(bwlq, type) \
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\
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static inline void writes##bwlq(volatile void __iomem *mem, \
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const void *addr, unsigned int count) \
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{ \
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const volatile type *__addr = addr; \
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\
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while (count--) { \
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__mem_write##bwlq(*__addr, mem); \
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__addr++; \
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} \
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} \
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\
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static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
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unsigned int count) \
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|
{ \
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volatile type *__addr = addr; \
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\
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while (count--) { \
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*__addr = __mem_read##bwlq(mem); \
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__addr++; \
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} \
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}
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|
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#define __BUILD_IOPORT_STRING(bwlq, type) \
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\
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static inline void outs##bwlq(unsigned long port, const void *addr, \
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unsigned int count) \
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|
{ \
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const volatile type *__addr = addr; \
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|
\
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while (count--) { \
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__mem_out##bwlq(*__addr, port); \
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__addr++; \
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} \
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|
} \
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|
\
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|
static inline void ins##bwlq(unsigned long port, void *addr, \
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|
unsigned int count) \
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|
{ \
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volatile type *__addr = addr; \
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\
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while (count--) { \
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*__addr = __mem_in##bwlq(port); \
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__addr++; \
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} \
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}
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|
|
#define BUILDSTRING(bwlq, type) \
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|
\
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__BUILD_MEMORY_STRING(bwlq, type) \
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__BUILD_IOPORT_STRING(bwlq, type)
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|
|
BUILDSTRING(b, u8)
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BUILDSTRING(w, u16)
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|
BUILDSTRING(l, u32)
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|
#ifdef CONFIG_64BIT
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BUILDSTRING(q, u64)
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|
#endif
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|
|
|
|
|
#ifdef CONFIG_CPU_CAVIUM_OCTEON
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#define mmiowb() wmb()
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#else
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/* Depends on MIPS II instruction set */
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|
#define mmiowb() asm volatile ("sync" ::: "memory")
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|
#endif
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|
|
static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
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|
{
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memset((void __force *)addr, val, count);
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}
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static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
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|
{
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memcpy(dst, (void __force *)src, count);
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}
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static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
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{
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memcpy((void __force *)dst, src, count);
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}
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|
|
/*
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* Read a 32-bit register that requires a 64-bit read cycle on the bus.
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* Avoid interrupt mucking, just adjust the address for 4-byte access.
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* Assume the addresses are 8-byte aligned.
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*/
|
|
#ifdef __MIPSEB__
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|
#define __CSR_32_ADJUST 4
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#else
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#define __CSR_32_ADJUST 0
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#endif
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|
#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
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#define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
|
|
|
|
/*
|
|
* U-Boot specific
|
|
*/
|
|
#define sync() mmiowb()
|
|
|
|
#define MAP_NOCACHE (1)
|
|
#define MAP_WRCOMBINE (0)
|
|
#define MAP_WRBACK (0)
|
|
#define MAP_WRTHROUGH (0)
|
|
|
|
static inline void *
|
|
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
|
|
{
|
|
if (flags == MAP_NOCACHE)
|
|
return ioremap(paddr, len);
|
|
|
|
return (void *)paddr;
|
|
}
|
|
|
|
/*
|
|
* Take down a mapping set up by map_physmem().
|
|
*/
|
|
static inline void unmap_physmem(void *vaddr, unsigned long flags)
|
|
{
|
|
}
|
|
|
|
#define __BUILD_CLRBITS(bwlq, sfx, end, type) \
|
|
\
|
|
static inline void clrbits_##sfx(volatile void __iomem *mem, type clr) \
|
|
{ \
|
|
type __val = __raw_read##bwlq(mem); \
|
|
__val = end##_to_cpu(__val); \
|
|
__val &= ~clr; \
|
|
__val = cpu_to_##end(__val); \
|
|
__raw_write##bwlq(__val, mem); \
|
|
}
|
|
|
|
#define __BUILD_SETBITS(bwlq, sfx, end, type) \
|
|
\
|
|
static inline void setbits_##sfx(volatile void __iomem *mem, type set) \
|
|
{ \
|
|
type __val = __raw_read##bwlq(mem); \
|
|
__val = end##_to_cpu(__val); \
|
|
__val |= set; \
|
|
__val = cpu_to_##end(__val); \
|
|
__raw_write##bwlq(__val, mem); \
|
|
}
|
|
|
|
#define __BUILD_CLRSETBITS(bwlq, sfx, end, type) \
|
|
\
|
|
static inline void clrsetbits_##sfx(volatile void __iomem *mem, \
|
|
type clr, type set) \
|
|
{ \
|
|
type __val = __raw_read##bwlq(mem); \
|
|
__val = end##_to_cpu(__val); \
|
|
__val &= ~clr; \
|
|
__val |= set; \
|
|
__val = cpu_to_##end(__val); \
|
|
__raw_write##bwlq(__val, mem); \
|
|
}
|
|
|
|
#define BUILD_CLRSETBITS(bwlq, sfx, end, type) \
|
|
\
|
|
__BUILD_CLRBITS(bwlq, sfx, end, type) \
|
|
__BUILD_SETBITS(bwlq, sfx, end, type) \
|
|
__BUILD_CLRSETBITS(bwlq, sfx, end, type)
|
|
|
|
#define __to_cpu(v) (v)
|
|
#define cpu_to__(v) (v)
|
|
|
|
BUILD_CLRSETBITS(b, 8, _, u8)
|
|
BUILD_CLRSETBITS(w, le16, le16, u16)
|
|
BUILD_CLRSETBITS(w, be16, be16, u16)
|
|
BUILD_CLRSETBITS(w, 16, _, u16)
|
|
BUILD_CLRSETBITS(l, le32, le32, u32)
|
|
BUILD_CLRSETBITS(l, be32, be32, u32)
|
|
BUILD_CLRSETBITS(l, 32, _, u32)
|
|
BUILD_CLRSETBITS(q, le64, le64, u64)
|
|
BUILD_CLRSETBITS(q, be64, be64, u64)
|
|
BUILD_CLRSETBITS(q, 64, _, u64)
|
|
|
|
#endif /* _ASM_IO_H */
|