York Sun 316f0d0f8f powerpc: mpc85xx: Fix static TLB table for SDRAM ... Most predefined TLB tables don't have memory coherence bit set for SDRAM. This wasn't an issue before invalidate_dcache_range() function was enabled. Without the coherence bit, dcache invalidation doesn't automatically flush the cache. The coherence bit is already set when dynamic TLB table is used. For some boards with different SPL boot method, or with legacy fixed setting, this bit needs to be set in TLB files. Signed-off-by: York Sun <york.sun@nxp.com>		2017-12-06 14:54:12 -08:00
..
cpld.c	powerpc/t4rdb: fix cpld reset altbank	2015-07-28 14:41:15 -07:00
cpld.h	powerpc/t4rdb: Add support of CPLD	2014-11-14 11:12:14 -08:00
ddr.c	board_f: Rename initdram() to dram_init()	2017-04-13 09:40:57 -04:00
ddr.h	board/freescale: Update ddr clk_adjust	2016-06-03 14:06:57 -07:00
eth.c	powerpc:t4240rdb: Disable the non-existent ethernet ports on T4240RDB	2016-05-24 17:11:03 -07:00
Kconfig	NXP: Introduce board/freescale/common/Kconfig and migrate CHAIN_OF_TRUST	2017-01-24 10:33:59 -05:00
law.c	powerpc/t4rdb: Add support of CPLD	2014-11-14 11:12:14 -08:00
MAINTAINERS	powerpc/t4rdb: Add SD boot support for T4240RDB board	2015-05-04 09:24:04 -07:00
Makefile	powerpc: T4240RDB: Remove macro CONFIG_T4240RDB	2016-11-23 23:42:15 -08:00
pci.c	powerpc/85xx: Add T4240RDB board support	2014-05-13 08:24:32 -07:00
spl.c	env: Add an enum for environment state	2017-08-15 08:18:51 -04:00
t4_pbi.cfg	pbl: use "wait" command instead of "flush" command	2016-10-14 10:21:30 -07:00
t4_sd_rcw.cfg	Txxx/RCW: Split unified RCW to RCWs for sd, spi and nand.	2016-10-14 10:21:03 -07:00
t4rdb.h	powerpc/85xx: Add T4240RDB board support	2014-05-13 08:24:32 -07:00
t4240rdb.c	env: Rename some other getenv()-related functions	2017-08-16 08:31:11 -04:00
tlb.c	powerpc: mpc85xx: Fix static TLB table for SDRAM	2017-12-06 14:54:12 -08:00