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https://github.com/AsahiLinux/u-boot
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b32e9a7578
Defines LS1028A RDB SGMII port, QDS RGMII port. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
321 lines
7.8 KiB
Text
321 lines
7.8 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP ls1028a SOC common device tree source
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*
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* Copyright 2019 NXP
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*
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*/
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/ {
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compatible = "fsl,ls1028a";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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sysclk: sysclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "sysclk";
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};
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clockgen: clocking@1300000 {
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compatible = "fsl,ls1028a-clockgen";
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reg = <0x0 0x1300000 0x0 0xa0000>;
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#clock-cells = <2>;
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clocks = <&sysclk>;
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};
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memory@01080000 {
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device_type = "memory";
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reg = <0x00000000 0x01080000 0 0x80000000>;
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/* DRAM space - 1, size : 2 GB DRAM */
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};
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gic: interrupt-controller@6000000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
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<0x0 0x06040000 0 0x40000>;
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <1 9 0x4>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
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<1 14 0x8>, /* Physical Non-Secure PPI, active-low */
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<1 11 0x8>, /* Virtual PPI, active-low */
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<1 10 0x8>; /* Hypervisor PPI, active-low */
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};
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fspi: flexspi@20C0000 {
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compatible = "nxp,dn-fspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x20C0000 0x0 0x10000>,
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<0x0 0x20000000 0x0 0x10000000>; /*64MB flash*/
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reg-names = "FSPI", "FSPI-memory";
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num-cs = <1>;
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status = "disabled";
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};
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serial0: serial@21c0500 {
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device_type = "serial";
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21c0500 0x0 0x100>;
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interrupts = <0 32 0x1>; /* edge triggered */
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status = "disabled";
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};
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serial1: serial@21c0600 {
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device_type = "serial";
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21c0600 0x0 0x100>;
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interrupts = <0 32 0x1>; /* edge triggered */
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status = "disabled";
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};
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pcie@3400000 {
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compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
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reg = <0x00 0x03400000 0x0 0x80000
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0x00 0x03480000 0x0 0x40000 /* lut registers */
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0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
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0x80 0x00000000 0x0 0x20000>; /* configuration space */
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reg-names = "dbi", "lut", "ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <4>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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};
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pcie@3500000 {
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compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
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reg = <0x00 0x03500000 0x0 0x80000
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0x00 0x03580000 0x0 0x40000 /* lut registers */
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0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
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0x88 0x00000000 0x0 0x20000>; /* configuration space */
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reg-names = "dbi", "lut", "ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <4>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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};
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pcie@1f0000000 {
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compatible = "pci-host-ecam-generic";
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/* ECAM bus 0, HW has more space reserved but not populated */
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bus-range = <0x0 0x0>;
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reg = <0x01 0xf0000000 0x0 0x100000>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges= <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>;
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enetc0: pci@0,0 {
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reg = <0x000000 0 0 0 0>;
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status = "disabled";
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};
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enetc1: pci@0,1 {
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reg = <0x000100 0 0 0 0>;
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status = "disabled";
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};
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enetc2: pci@0,2 {
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reg = <0x000200 0 0 0 0>;
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status = "okay";
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phy-mode = "internal";
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};
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mdio0: pci@0,3 {
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#address-cells=<0>;
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#size-cells=<1>;
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reg = <0x000300 0 0 0 0>;
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status = "disabled";
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};
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enetc6: pci@0,6 {
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reg = <0x000600 0 0 0 0>;
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status = "okay";
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phy-mode = "internal";
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};
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};
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i2c0: i2c@2000000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2000000 0x0 0x10000>;
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interrupts = <0 34 0x4>;
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clock-names = "i2c";
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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i2c1: i2c@2010000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2010000 0x0 0x10000>;
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interrupts = <0 34 0x4>;
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clock-names = "i2c";
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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i2c2: i2c@2020000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2020000 0x0 0x10000>;
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interrupts = <0 35 0x4>;
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clock-names = "i2c";
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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i2c3: i2c@2030000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2030000 0x0 0x10000>;
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interrupts = <0 35 0x4>;
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clock-names = "i2c";
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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i2c4: i2c@2040000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2040000 0x0 0x10000>;
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interrupts = <0 74 0x4>;
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clock-names = "i2c";
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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i2c5: i2c@2050000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2050000 0x0 0x10000>;
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interrupts = <0 74 0x4>;
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clock-names = "i2c";
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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i2c6: i2c@2060000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2060000 0x0 0x10000>;
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interrupts = <0 75 0x4>;
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clock-names = "i2c";
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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i2c7: i2c@2070000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2070000 0x0 0x10000>;
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interrupts = <0 75 0x4>;
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clock-names = "i2c";
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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usb1: usb3@3100000 {
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compatible = "fsl,layerscape-dwc3";
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reg = <0x0 0x3100000 0x0 0x10000>;
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interrupts = <0 80 0x4>;
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dr_mode = "host";
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status = "disabled";
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};
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usb2: usb3@3110000 {
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compatible = "fsl,layerscape-dwc3";
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reg = <0x0 0x3110000 0x0 0x10000>;
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interrupts = <0 81 0x4>;
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dr_mode = "host";
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status = "disabled";
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};
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dspi0: dspi@2100000 {
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compatible = "fsl,vf610-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2100000 0x0 0x10000>;
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interrupts = <0 26 0x4>;
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clock-names = "dspi";
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clocks = <&clockgen 4 0>;
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num-cs = <5>;
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litte-endian;
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status = "disabled";
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};
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dspi1: dspi@2110000 {
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compatible = "fsl,vf610-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2110000 0x0 0x10000>;
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interrupts = <0 26 0x4>;
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clock-names = "dspi";
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clocks = <&clockgen 4 0>;
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num-cs = <5>;
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little-endian;
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status = "disabled";
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};
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dspi2: dspi@2120000 {
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compatible = "fsl,vf610-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2120000 0x0 0x10000>;
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interrupts = <0 26 0x4>;
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clock-names = "dspi";
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clocks = <&clockgen 4 0>;
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num-cs = <5>;
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little-endian;
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status = "disabled";
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};
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esdhc0: esdhc@2140000 {
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compatible = "fsl,esdhc";
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reg = <0x0 0x2140000 0x0 0x10000>;
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interrupts = <0 28 0x4>;
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big-endian;
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bus-width = <4>;
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status = "disabled";
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};
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esdhc1: esdhc@2150000 {
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compatible = "fsl,esdhc";
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reg = <0x0 0x2150000 0x0 0x10000>;
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interrupts = <0 63 0x4>;
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big-endian;
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non-removable;
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bus-width = <4>;
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status = "disabled";
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};
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sata: sata@3200000 {
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compatible = "fsl,ls1028a-ahci";
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reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
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0x7 0x100520 0x0 0x4>; /* ecc sata addr*/
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reg-names = "sata-base", "ecc-addr";
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interrupts = <0 133 4>;
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status = "disabled";
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};
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cluster1_core0_watchdog: wdt@c000000 {
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compatible = "arm,sp805-wdt";
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reg = <0x0 0xc000000 0x0 0x1000>;
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};
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};
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