u-boot/drivers/clk/at91/Kconfig
Wenyou Yang 6cadaa046b clk: at91: Improve the clock implementation
For the peripheral clock, provide the clock ops for the clock
provider, such as spi0_clk. The .of_xlate is to get the clk->id,
the .enable is to enable the spi0 peripheral clock, the .get_rate
is to get the clock frequency.

The driver for periph32ck node is responsible for recursively
binding its children as clk devices, not provide the clock ops.

So do the generated clock and system clock.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2016-10-28 18:37:14 +02:00

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config CLK_AT91
bool "AT91 clock drivers"
depends on CLK
select MISC
help
This option is used to enable the AT91 clock driver.
The driver supports the AT91 clock generator, including
the oscillators and PLLs, such as main clock, slow clock,
PLLA, UTMI PLL. Clocks can also be a source clock of other
clocks a tree structure, such as master clock, usb device
clock, matrix clock and generic clock.
Devices can use a common clock API to request a particular
clock, enable it and get its rate.
config AT91_UTMI
bool "Support UTMI PLL Clock"
depends on CLK_AT91
help
This option is used to enable the AT91 UTMI PLL clock
driver. It is the clock provider of USB, and UPLLCK is the
output of 480 MHz UTMI PLL, The souce clock of the UTMI
PLL is the main clock, so the main clock must select the
fast crystal oscillator to meet the frequency accuracy
required by USB.
config AT91_H32MX
bool "Support H32MX 32-bit Matrix Clock"
depends on CLK_AT91
help
This option is used to enable the AT91 H32MX matrixes
clock driver. There are H64MX and H32MX matrixes clocks,
H64MX 64-bit matrix clocks are MCK. The H32MX 32-bit
matrix clock is to be configured as MCK if MCK does not
exceed 83 MHz, else it is to be configured as MCK/2.
config AT91_GENERIC_CLK
bool "Support Generic Clock"
depends on CLK_AT91
help
This option is used to enable the AT91 generic clock
driver. Some peripherals may need a second clock source
that may be different from the system clock. This second
clock is the generic clock (GCLK) and is managed by
the PMC via PMC_PCR register.