mirror of
https://github.com/AsahiLinux/u-boot
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3135ba642f
There are no platforms that set this, remove the code. Signed-off-by: Tom Rini <trini@konsulko.com>
98 lines
2.5 KiB
ArmAsm
98 lines
2.5 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* armboot - Startup Code for XScale CPU-core
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*
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* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
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* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
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* Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
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* Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
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* Copyright (C) 2001 Marius Groger <mag@sysgo.de>
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* Copyright (C) 2002 Alex Zupke <azu@sysgo.de>
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* Copyright (C) 2002 Gary Jennejohn <garyj@denx.de>
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* Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
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* Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
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* Copyright (C) 2003 Kshitij <kshitij@ti.com>
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* Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com>
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* Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
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* Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com>
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* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
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*/
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#include <asm-offsets.h>
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#include <config.h>
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/*
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*************************************************************************
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*
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* Startup Code (reset vector)
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*
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* do important init only if we don't start from memory!
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* setup Memory and board specific bits prior to relocation.
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* relocate armboot to ram
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* setup stack
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*
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*************************************************************************
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*/
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.globl reset
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reset:
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/*
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* set the cpu to SVC32 mode
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*/
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mrs r0,cpsr
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bic r0,r0,#0x1f
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orr r0,r0,#0xd3
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msr cpsr,r0
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
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bl cpu_init_crit
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#endif
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#ifdef CONFIG_CPU_PXA27X
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/*
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* enable clock for SRAM
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*/
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ldr r0,=CKEN
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ldr r1,[r0]
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orr r1,r1,#(1 << 20)
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str r1,[r0]
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#endif
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bl _main
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/*------------------------------------------------------------------------------*/
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.globl c_runtime_cpu_setup
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c_runtime_cpu_setup:
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bx lr
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/*
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*************************************************************************
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*
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* CPU_init_critical registers
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*
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* setup important registers
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* setup memory timing
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*
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*************************************************************************
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*/
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
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cpu_init_crit:
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/*
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* flush v4 I/D caches
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*/
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
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mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
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/*
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* disable MMU stuff and caches
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00003300 @ clear bits 13:12, 9:8 (--VI --RS)
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bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
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orr r0, r0, #0x00000002 @ set bit 1 (A) Align
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mcr p15, 0, r0, c1, c0, 0
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mov pc, lr /* back to my caller */
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#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
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