mirror of
https://github.com/AsahiLinux/u-boot
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323d1f9d5b
Before this commit, the Kconfig menu in mach-uniphier only allowed us
to choose one SoC to be compiled. Each SoC has its own defconfig file
for the build-test coverage. Consequently, some defconfig files are
duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and
CONFIG_{SOC_NAME}=y.
Now, most of board-specific parameters have been moved to device trees,
so it makes sense to include init code of multiple SoCs into a single
image as long as the SoCs have similar architecture. In fact, some
SoCs of UniPhier family are very similar:
- PH1-LD4 and PH1-sLD8
- PH1-LD6b and ProXstream2 (will be added in the upcoming commit)
This commit will be helpful to merge some defconfig files for better
maintainability.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
52 lines
1.3 KiB
C
52 lines
1.3 KiB
C
/*
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* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/io.h>
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#include <mach/init.h>
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#include <mach/sbc-regs.h>
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#include <mach/sg-regs.h>
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int ph1_ld4_sbc_init(const struct uniphier_board_data *bd)
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{
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u32 tmp;
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/* system bus output enable */
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tmp = readl(PC0CTRL);
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tmp &= 0xfffffcff;
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writel(tmp, PC0CTRL);
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/*
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* Only CS1 is connected to support card.
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* BKSZ[1:0] should be set to "01".
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*/
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writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
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writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
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writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
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writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
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if (boot_is_swapped()) {
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/*
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* Boot Swap On: boot from external NOR/SRAM
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* 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
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*
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* 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
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* 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
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*/
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writel(0x0000bc01, SBBASE0);
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} else {
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/*
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* Boot Swap Off: boot from mask ROM
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* 0x40000000-0x41ffffff: mask ROM
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* 0x42000000-0x43efffff: memory bank (31MB)
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* 0x43f00000-0x43ffffff: peripherals (1MB)
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*/
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writel(0x0000be01, SBBASE0); /* dummy */
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writel(0x0200be01, SBBASE1);
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}
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return 0;
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}
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