u-boot/arch/arc/lib/cpu.c
Alexey Brodkin ef639e6f70 arc: significant cache rework
[1] Align cache management functions to those in Linux kernel. I.e.:
    a) Use the same functions for all cache ops (D$ Inv/Flush)
    b) Split cache ops in 3 sub-functions: "before", "lineloop" and
"after". That way we may re-use "before" and "after" functions for
region and full cache ops.

 [2] Implement full-functional L2 (SLC) management. Before SLC was
simply disabled early on boot. It's also possible to enable or disable
L2 cache from config utility.

 [3] Disable/enable corresponding caches early on boot. So if U-Boot is
configured to use caches they will be used at all times (this is useful
in partucular for speed-up of relocation).

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-07-01 17:17:27 +03:00

36 lines
682 B
C

/*
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arcregs.h>
#include <asm/cache.h>
DECLARE_GLOBAL_DATA_PTR;
int arch_cpu_init(void)
{
timer_init();
/* In simulation (ISS) "CHIPID" and "ARCNUM" are all "ff" */
if ((read_aux_reg(ARC_AUX_IDENTITY) & 0xffffff00) == 0xffffff00)
gd->arch.running_on_hw = 0;
else
gd->arch.running_on_hw = 1;
gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
cache_init();
return 0;
}
int arch_early_init_r(void)
{
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
return 0;
}