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The 8572 DDR erratum1: DDR controller may enter an illegal state when operating in 32-bit bus mode with 4-beat bursts. Description: When operating with a 32-bit bus, it is recommended that DDR_SDRAM_CFG[8_BE] is cleared when DDR2 memories are used. This forces the DDR controller to use 4-beat bursts when communicating to the DRAMs. However, an issue exists that could lead to data corruption when the DDR controller is in 32-bit bus mode while using 4-beat bursts. Projected Impact: If the DDR controller is operating in 32-bit bus mode with 4-beat bursts, then the controller may enter into a bad state. All subsequent reads from memory is corrupted. Four-beat bursts with a 32-bit bus only is used with DDR2 memories. Therefore, this erratum does not affect DDR3 mode. Work Arounds: To work around this issue, software must set DEBUG_1[31] in DDR memory mapped space (CCSRBAR offset + 0x2f00 for DDR_1 and CCSRBAR offset + 0x6f00 for DDR_2). Currenlty, the code is using incorrect register DDR_SDRAM_CFG_2 as condition, but it should be DDR_SDRAM_CFG register. Signed-off-by: Dave Liu <daveliu@freescale.com> |
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| .. | ||
| commproc.c | ||
| config.mk | ||
| cpu.c | ||
| cpu_init.c | ||
| ddr-gen1.c | ||
| ddr-gen2.c | ||
| ddr-gen3.c | ||
| ether_fcc.c | ||
| fdt.c | ||
| interrupts.c | ||
| Makefile | ||
| mp.c | ||
| mp.h | ||
| mpc8536_serdes.c | ||
| pci.c | ||
| qe_io.c | ||
| release.S | ||
| resetvec.S | ||
| serial_scc.c | ||
| speed.c | ||
| start.S | ||
| tlb.c | ||
| traps.c | ||