u-boot/arch/arm/cpu/arm926ejs/davinci/et1011c.c
Sandeep Paulraj 840f8923a0 DaVinci DM6467: Added ET1011C (LSI) PHY support
Added arch/arm/cpu/arm926ejs/davinci/et1011c.c for handling
ET1011C gigabit phy. which overrides get_link_speed function
from default implementation. This enables output of 125 MHz
reference clock on SYS_CLK pin.

Signed-off-by: Prakash PM <prakash.pm@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-02-02 00:54:44 +01:00

55 lines
1.5 KiB
C

/*
* LSI ET1011C PHY Driver for TI DaVinci(TMS320DM6467) board.
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <common.h>
#include <net.h>
#include <miiphy.h>
#include <asm/arch/emac_defs.h>
#ifdef CONFIG_DRIVER_TI_EMAC
#ifdef CONFIG_CMD_NET
/* LSI PHYSICAL LAYER TRANSCEIVER ET1011C */
#define MII_PHY_CONFIG_REG 22
/* PHY Config bits */
#define PHY_SYS_CLK_EN (1 << 4)
int et1011c_get_link_speed(int phy_addr)
{
u_int16_t data;
if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &data) && (data & 0x04)) {
davinci_eth_phy_read(EMAC_MDIO_PHY_NUM,
MII_PHY_CONFIG_REG, &data);
/* Enable 125MHz clock sourced from PHY */
davinci_eth_phy_write(EMAC_MDIO_PHY_NUM,
MII_PHY_CONFIG_REG,
data | PHY_SYS_CLK_EN);
return (1);
}
return (0);
}
#endif /* CONFIG_CMD_NET */
#endif /* CONFIG_DRIVER_ETHER */