mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-15 09:27:35 +00:00
6d36e92d28
Add support for Kevin, an RK3399-based convertible chromebook that is
very similar to Bob. This patch is mostly based on existing support for
Bob, with only minor changes for Kevin-specific things.
Unlike other Gru boards, coreboot sets Kevin's center logic to 925 mV,
so adjust it here in the dts as well. The rk3399-gru-kevin devicetree
has an unknown event code reference which has to be defined, set it
to the Linux counterpart. The new defconfig is copied from Bob with the
diffconfig:
DEFAULT_DEVICE_TREE "rk3399-gru-bob" -> "rk3399-gru-kevin"
DEFAULT_FDT_FILE "rockchip/rk3399-gru-bob.dtb" -> "rockchip/rk3399-gru-kevin.dtb"
VIDEO_ROCKCHIP_MAX_XRES 1280 -> 2400
VIDEO_ROCKCHIP_MAX_YRES 800 -> 1600
+TARGET_CHROMEBOOK_KEVIN y
With this Kevin can boot from SPI flash to a usable U-Boot prompt on the
display with the keyboard working, but cannot boot into Linux for
unknown reasons.
eMMC starts in a working state but fails to re-init, microSD card works
but at a lower-than-expected speed, USB works but causes a hang on
de-init. There are known workarounds to solve eMMC and USB issues.
Cc: Marty E. Plummer <hanetzer@startmail.com>
Cc: Simon Glass <sjg@chromium.org>
[Alper: commit message, resync config with Bob, update MAINTAINERS,
add to Rockchip doc, add Kconfig help message, set regulator]
Co-developed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
108 lines
2.4 KiB
C
108 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 Google
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*/
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#include <common.h>
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#include <dm.h>
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#include <init.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/grf_rk3399.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <asm/arch-rockchip/misc.h>
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#define GRF_IO_VSEL_BT656_SHIFT 0
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#define GRF_IO_VSEL_AUDIO_SHIFT 1
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#define PMUGRF_CON0_VSEL_SHIFT 8
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#define PMUGRF_CON0_VOL_SHIFT 9
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#ifdef CONFIG_SPL_BUILD
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/* provided to defeat compiler optimisation in board_init_f() */
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void gru_dummy_function(int i)
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{
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}
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int board_early_init_f(void)
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{
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# if defined(CONFIG_TARGET_CHROMEBOOK_BOB) || defined(CONFIG_TARGET_CHROMEBOOK_KEVIN)
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int sum, i;
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/*
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* Add a delay and ensure that the compiler does not optimise this out.
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* This is needed since the power rails tail a while to turn on, and
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* we get garbage serial output otherwise.
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*/
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sum = 0;
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for (i = 0; i < 150000; i++)
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sum += i;
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gru_dummy_function(sum);
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#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
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return 0;
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}
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#endif
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#ifndef CONFIG_SPL_BUILD
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int board_early_init_r(void)
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{
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struct udevice *clk;
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int ret;
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/*
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* This init is done in SPL, but when chain-loading U-Boot SPL will
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* have been skipped. Allow the clock driver to check if it needs
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* setting up.
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*/
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ret = uclass_get_device_by_driver(UCLASS_CLK,
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DM_DRIVER_GET(clk_rk3399), &clk);
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if (ret) {
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debug("%s: CLK init failed: %d\n", __func__, ret);
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return ret;
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}
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return 0;
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}
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#endif
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static void setup_iodomain(void)
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{
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struct rk3399_grf_regs *grf =
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syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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struct rk3399_pmugrf_regs *pmugrf =
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syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
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/* BT656 and audio is in 1.8v domain */
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rk_setreg(&grf->io_vsel, (1 << GRF_IO_VSEL_BT656_SHIFT |
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1 << GRF_IO_VSEL_AUDIO_SHIFT));
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/*
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* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL
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* and explicitly configure that PMU1830_VOL to be 1.8V
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*/
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rk_setreg(&pmugrf->soc_con0, (1 << PMUGRF_CON0_VSEL_SHIFT |
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1 << PMUGRF_CON0_VOL_SHIFT));
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}
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int misc_init_r(void)
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{
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const u32 cpuid_offset = 0x7;
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const u32 cpuid_length = 0x10;
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u8 cpuid[cpuid_length];
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int ret;
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setup_iodomain();
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ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
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if (ret)
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return ret;
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ret = rockchip_cpuid_set(cpuid, cpuid_length);
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if (ret)
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return ret;
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ret = rockchip_setup_macaddr();
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return ret;
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}
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