mirror of
https://github.com/AsahiLinux/u-boot
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dcf2cee77f
The driver is based on the Versaclock driver from the Linux code, but due differences in the clock API between them, some pieces had to be changed. This driver creates a mux, pfd, pll, and a series of fod ouputs. Rate Usecnt Name ------------------------------------------ 25000000 0 `-- x304-clock 25000000 0 `-- clock-controller@6a.mux 25000000 0 |-- clock-controller@6a.pfd 2800000000 0 | `-- clock-controller@6a.pll 33333333 0 | |-- clock-controller@6a.fod0 33333333 0 | | `-- clock-controller@6a.out1 33333333 0 | |-- clock-controller@6a.fod1 33333333 0 | | `-- clock-controller@6a.out2 50000000 0 | |-- clock-controller@6a.fod2 50000000 0 | | `-- clock-controller@6a.out3 125000000 0 | `-- clock-controller@6a.fod3 125000000 0 | `-- clock-controller@6a.out4 25000000 0 `-- clock-controller@6a.out0_sel_i2cb A translation function is added so the references to <&versaclock X> get routed to the corresponding clock-controller@6a.outX. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Sean Anderson <sean.anderson@seco.com>
55 lines
2 KiB
Makefile
55 lines
2 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (c) 2015 Google, Inc
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o
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obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o
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obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o
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obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-divider.o clk-mux.o clk-gate.o
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obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk-fixed-factor.o
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obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o
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obj-y += analogbits/
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obj-y += imx/
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obj-y += tegra/
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obj-y += ti/
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obj-$(CONFIG_ARCH_ASPEED) += aspeed/
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obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
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obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
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obj-$(CONFIG_ARCH_MESON) += meson/
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obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
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obj-$(CONFIG_ARCH_SOCFPGA) += altera/
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obj-$(CONFIG_CLK_AT91) += at91/
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obj-$(CONFIG_CLK_MVEBU) += mvebu/
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obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
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obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
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obj-$(CONFIG_CLK_EXYNOS) += exynos/
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obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
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obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
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obj-$(CONFIG_CLK_K210) += clk_kendryte.o
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obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
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obj-$(CONFIG_CLK_MPFS) += microchip/
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obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o
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obj-$(CONFIG_CLK_OWL) += owl/
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obj-$(CONFIG_CLK_RENESAS) += renesas/
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obj-$(CONFIG_CLK_SCMI) += clk_scmi.o
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obj-$(CONFIG_CLK_SIFIVE) += sifive/
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obj-$(CONFIG_ARCH_SUNXI) += sunxi/
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obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
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obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
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obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
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obj-$(CONFIG_CLK_VEXPRESS_OSC) += clk_vexpress_osc.o
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obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
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obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
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obj-$(CONFIG_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o
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obj-$(CONFIG_ICS8N3QV01) += ics8n3qv01.o
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obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
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obj-$(CONFIG_SANDBOX) += clk_sandbox.o
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obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
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obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o
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obj-$(CONFIG_STM32H7) += clk_stm32h7.o
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obj-$(CONFIG_CLK_VERSAL) += clk_versal.o
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obj-$(CONFIG_CLK_CDCE9XX) += clk-cdce9xx.o
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obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o
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