mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-19 11:18:28 +00:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
719 lines
19 KiB
C
719 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012 Samsung Electronics
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*
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* Author: InKi Dae <inki.dae@samsung.com>
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* Author: Donghwa Lee <dh09.lee@samsung.com>
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*/
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#include <config.h>
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#include <common.h>
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#include <display.h>
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#include <div64.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <linux/libfdt.h>
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#include <panel.h>
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#include <video.h>
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#include <video_bridge.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/mipi_dsim.h>
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#include <asm/arch/dp_info.h>
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#include <asm/arch/fb.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/system.h>
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#include <asm/gpio.h>
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#include <linux/errno.h>
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DECLARE_GLOBAL_DATA_PTR;
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enum {
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FIMD_RGB_INTERFACE = 1,
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FIMD_CPU_INTERFACE = 2,
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};
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enum exynos_fb_rgb_mode_t {
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MODE_RGB_P = 0,
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MODE_BGR_P = 1,
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MODE_RGB_S = 2,
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MODE_BGR_S = 3,
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};
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struct exynos_fb_priv {
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ushort vl_col; /* Number of columns (i.e. 640) */
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ushort vl_row; /* Number of rows (i.e. 480) */
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ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */
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ushort vl_width; /* Width of display area in millimeters */
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ushort vl_height; /* Height of display area in millimeters */
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/* LCD configuration register */
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u_char vl_freq; /* Frequency */
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u_char vl_clkp; /* Clock polarity */
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u_char vl_oep; /* Output Enable polarity */
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u_char vl_hsp; /* Horizontal Sync polarity */
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u_char vl_vsp; /* Vertical Sync polarity */
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u_char vl_dp; /* Data polarity */
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u_char vl_bpix; /* Bits per pixel */
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/* Horizontal control register. Timing from data sheet */
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u_char vl_hspw; /* Horz sync pulse width */
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u_char vl_hfpd; /* Wait before of line */
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u_char vl_hbpd; /* Wait end of line */
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/* Vertical control register. */
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u_char vl_vspw; /* Vertical sync pulse width */
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u_char vl_vfpd; /* Wait before of frame */
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u_char vl_vbpd; /* Wait end of frame */
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u_char vl_cmd_allow_len; /* Wait end of frame */
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unsigned int win_id;
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unsigned int init_delay;
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unsigned int power_on_delay;
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unsigned int reset_delay;
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unsigned int interface_mode;
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unsigned int mipi_enabled;
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unsigned int dp_enabled;
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unsigned int cs_setup;
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unsigned int wr_setup;
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unsigned int wr_act;
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unsigned int wr_hold;
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unsigned int logo_on;
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unsigned int logo_width;
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unsigned int logo_height;
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int logo_x_offset;
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int logo_y_offset;
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unsigned long logo_addr;
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unsigned int rgb_mode;
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unsigned int resolution;
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/* parent clock name(MPLL, EPLL or VPLL) */
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unsigned int pclk_name;
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/* ratio value for source clock from parent clock. */
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unsigned int sclk_div;
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unsigned int dual_lcd_enabled;
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struct exynos_fb *reg;
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struct exynos_platform_mipi_dsim *dsim_platform_data_dt;
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};
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static void exynos_fimd_set_dualrgb(struct exynos_fb_priv *priv, bool enabled)
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{
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struct exynos_fb *reg = priv->reg;
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unsigned int cfg = 0;
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if (enabled) {
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cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT |
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EXYNOS_DUALRGB_VDEN_EN_ENABLE;
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/* in case of Line Split mode, MAIN_CNT doesn't neet to set. */
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cfg |= EXYNOS_DUALRGB_SUB_CNT(priv->vl_col / 2) |
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EXYNOS_DUALRGB_MAIN_CNT(0);
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}
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writel(cfg, ®->dualrgb);
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}
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static void exynos_fimd_set_dp_clkcon(struct exynos_fb_priv *priv,
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unsigned int enabled)
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{
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struct exynos_fb *reg = priv->reg;
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unsigned int cfg = 0;
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if (enabled)
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cfg = EXYNOS_DP_CLK_ENABLE;
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writel(cfg, ®->dp_mie_clkcon);
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}
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static void exynos_fimd_set_par(struct exynos_fb_priv *priv,
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unsigned int win_id)
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{
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struct exynos_fb *reg = priv->reg;
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unsigned int cfg = 0;
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/* set window control */
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cfg = readl((unsigned int)®->wincon0 +
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EXYNOS_WINCON(win_id));
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cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE |
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EXYNOS_WINCON_HAWSWP_ENABLE | EXYNOS_WINCON_WSWP_ENABLE |
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EXYNOS_WINCON_BURSTLEN_MASK | EXYNOS_WINCON_BPPMODE_MASK |
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EXYNOS_WINCON_INRGB_MASK | EXYNOS_WINCON_DATAPATH_MASK);
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/* DATAPATH is DMA */
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cfg |= EXYNOS_WINCON_DATAPATH_DMA;
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cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
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/* dma burst is 16 */
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cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
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switch (priv->vl_bpix) {
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case 4:
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cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
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break;
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default:
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cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
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break;
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}
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writel(cfg, (unsigned int)®->wincon0 +
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EXYNOS_WINCON(win_id));
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/* set window position to x=0, y=0*/
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cfg = EXYNOS_VIDOSD_LEFT_X(0) | EXYNOS_VIDOSD_TOP_Y(0);
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writel(cfg, (unsigned int)®->vidosd0a +
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EXYNOS_VIDOSD(win_id));
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cfg = EXYNOS_VIDOSD_RIGHT_X(priv->vl_col - 1) |
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EXYNOS_VIDOSD_BOTTOM_Y(priv->vl_row - 1) |
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EXYNOS_VIDOSD_RIGHT_X_E(1) |
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EXYNOS_VIDOSD_BOTTOM_Y_E(0);
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writel(cfg, (unsigned int)®->vidosd0b +
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EXYNOS_VIDOSD(win_id));
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/* set window size for window0*/
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cfg = EXYNOS_VIDOSD_SIZE(priv->vl_col * priv->vl_row);
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writel(cfg, (unsigned int)®->vidosd0c +
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EXYNOS_VIDOSD(win_id));
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}
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static void exynos_fimd_set_buffer_address(struct exynos_fb_priv *priv,
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unsigned int win_id,
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ulong lcd_base_addr)
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{
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struct exynos_fb *reg = priv->reg;
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unsigned long start_addr, end_addr;
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start_addr = lcd_base_addr;
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end_addr = start_addr + ((priv->vl_col * (VNBITS(priv->vl_bpix) / 8)) *
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priv->vl_row);
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writel(start_addr, (unsigned int)®->vidw00add0b0 +
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EXYNOS_BUFFER_OFFSET(win_id));
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writel(end_addr, (unsigned int)®->vidw00add1b0 +
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EXYNOS_BUFFER_OFFSET(win_id));
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}
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static void exynos_fimd_set_clock(struct exynos_fb_priv *priv)
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{
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struct exynos_fb *reg = priv->reg;
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unsigned int cfg = 0, div = 0, remainder, remainder_div;
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unsigned long pixel_clock;
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unsigned long long src_clock;
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if (priv->dual_lcd_enabled) {
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pixel_clock = priv->vl_freq *
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(priv->vl_hspw + priv->vl_hfpd +
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priv->vl_hbpd + priv->vl_col / 2) *
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(priv->vl_vspw + priv->vl_vfpd +
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priv->vl_vbpd + priv->vl_row);
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} else if (priv->interface_mode == FIMD_CPU_INTERFACE) {
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pixel_clock = priv->vl_freq *
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priv->vl_width * priv->vl_height *
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(priv->cs_setup + priv->wr_setup +
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priv->wr_act + priv->wr_hold + 1);
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} else {
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pixel_clock = priv->vl_freq *
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(priv->vl_hspw + priv->vl_hfpd +
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priv->vl_hbpd + priv->vl_col) *
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(priv->vl_vspw + priv->vl_vfpd +
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priv->vl_vbpd + priv->vl_row);
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}
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cfg = readl(®->vidcon0);
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cfg &= ~(EXYNOS_VIDCON0_CLKSEL_MASK | EXYNOS_VIDCON0_CLKVALUP_MASK |
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EXYNOS_VIDCON0_CLKVAL_F(0xFF) | EXYNOS_VIDCON0_VCLKEN_MASK |
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EXYNOS_VIDCON0_CLKDIR_MASK);
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cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS |
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EXYNOS_VIDCON0_VCLKEN_NORMAL | EXYNOS_VIDCON0_CLKDIR_DIVIDED);
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src_clock = (unsigned long long) get_lcd_clk();
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/* get quotient and remainder. */
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remainder = do_div(src_clock, pixel_clock);
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div = src_clock;
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remainder *= 10;
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remainder_div = remainder / pixel_clock;
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/* round about one places of decimals. */
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if (remainder_div >= 5)
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div++;
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/* in case of dual lcd mode. */
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if (priv->dual_lcd_enabled)
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div--;
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cfg |= EXYNOS_VIDCON0_CLKVAL_F(div - 1);
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writel(cfg, ®->vidcon0);
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}
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void exynos_set_trigger(struct exynos_fb_priv *priv)
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{
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struct exynos_fb *reg = priv->reg;
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unsigned int cfg = 0;
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cfg = readl(®->trigcon);
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cfg |= (EXYNOS_I80SOFT_TRIG_EN | EXYNOS_I80START_TRIG);
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writel(cfg, ®->trigcon);
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}
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int exynos_is_i80_frame_done(struct exynos_fb_priv *priv)
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{
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struct exynos_fb *reg = priv->reg;
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unsigned int cfg = 0;
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int status;
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cfg = readl(®->trigcon);
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/* frame done func is valid only when TRIMODE[0] is set to 1. */
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status = (cfg & EXYNOS_I80STATUS_TRIG_DONE) ==
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EXYNOS_I80STATUS_TRIG_DONE;
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return status;
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}
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static void exynos_fimd_lcd_on(struct exynos_fb_priv *priv)
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{
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struct exynos_fb *reg = priv->reg;
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unsigned int cfg = 0;
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/* display on */
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cfg = readl(®->vidcon0);
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cfg |= (EXYNOS_VIDCON0_ENVID_ENABLE | EXYNOS_VIDCON0_ENVID_F_ENABLE);
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writel(cfg, ®->vidcon0);
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}
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static void exynos_fimd_window_on(struct exynos_fb_priv *priv,
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unsigned int win_id)
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{
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struct exynos_fb *reg = priv->reg;
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unsigned int cfg = 0;
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/* enable window */
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cfg = readl((unsigned int)®->wincon0 +
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EXYNOS_WINCON(win_id));
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cfg |= EXYNOS_WINCON_ENWIN_ENABLE;
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writel(cfg, (unsigned int)®->wincon0 +
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EXYNOS_WINCON(win_id));
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cfg = readl(®->winshmap);
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cfg |= EXYNOS_WINSHMAP_CH_ENABLE(win_id);
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writel(cfg, ®->winshmap);
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}
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void exynos_fimd_lcd_off(struct exynos_fb_priv *priv)
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{
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struct exynos_fb *reg = priv->reg;
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unsigned int cfg = 0;
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cfg = readl(®->vidcon0);
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cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE);
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writel(cfg, ®->vidcon0);
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}
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void exynos_fimd_window_off(struct exynos_fb_priv *priv, unsigned int win_id)
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{
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struct exynos_fb *reg = priv->reg;
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unsigned int cfg = 0;
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cfg = readl((unsigned int)®->wincon0 +
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EXYNOS_WINCON(win_id));
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cfg &= EXYNOS_WINCON_ENWIN_DISABLE;
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writel(cfg, (unsigned int)®->wincon0 +
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EXYNOS_WINCON(win_id));
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cfg = readl(®->winshmap);
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cfg &= ~EXYNOS_WINSHMAP_CH_DISABLE(win_id);
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writel(cfg, ®->winshmap);
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}
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/*
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* The reset value for FIMD SYSMMU register MMU_CTRL is 3
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* on Exynos5420 and newer versions.
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* This means FIMD SYSMMU is on by default on Exynos5420
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* and newer versions.
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* Since in u-boot we don't use SYSMMU, we should disable
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* those FIMD SYSMMU.
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* Note that there are 2 SYSMMU for FIMD: m0 and m1.
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* m0 handles windows 0 and 4, and m1 handles windows 1, 2 and 3.
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* We disable both of them here.
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*/
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void exynos_fimd_disable_sysmmu(void)
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{
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u32 *sysmmufimd;
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unsigned int node;
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int node_list[2];
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int count;
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int i;
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count = fdtdec_find_aliases_for_id(gd->fdt_blob, "fimd",
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COMPAT_SAMSUNG_EXYNOS_SYSMMU, node_list, 2);
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for (i = 0; i < count; i++) {
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node = node_list[i];
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if (node <= 0) {
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debug("Can't get device node for fimd sysmmu\n");
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return;
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}
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sysmmufimd = (u32 *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
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if (!sysmmufimd) {
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debug("Can't get base address for sysmmu fimdm0");
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return;
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}
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writel(0x0, sysmmufimd);
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}
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}
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void exynos_fimd_lcd_init(struct udevice *dev)
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{
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struct exynos_fb_priv *priv = dev_get_priv(dev);
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struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
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struct exynos_fb *reg = priv->reg;
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unsigned int cfg = 0, rgb_mode;
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unsigned int offset;
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unsigned int node;
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node = dev_of_offset(dev);
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if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu"))
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exynos_fimd_disable_sysmmu();
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offset = exynos_fimd_get_base_offset();
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rgb_mode = priv->rgb_mode;
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if (priv->interface_mode == FIMD_RGB_INTERFACE) {
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cfg |= EXYNOS_VIDCON0_VIDOUT_RGB;
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writel(cfg, ®->vidcon0);
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cfg = readl(®->vidcon2);
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cfg &= ~(EXYNOS_VIDCON2_WB_MASK |
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EXYNOS_VIDCON2_TVFORMATSEL_MASK |
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EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK);
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cfg |= EXYNOS_VIDCON2_WB_DISABLE;
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writel(cfg, ®->vidcon2);
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/* set polarity */
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cfg = 0;
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if (!priv->vl_clkp)
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cfg |= EXYNOS_VIDCON1_IVCLK_RISING_EDGE;
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if (!priv->vl_hsp)
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cfg |= EXYNOS_VIDCON1_IHSYNC_INVERT;
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if (!priv->vl_vsp)
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cfg |= EXYNOS_VIDCON1_IVSYNC_INVERT;
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if (!priv->vl_dp)
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cfg |= EXYNOS_VIDCON1_IVDEN_INVERT;
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writel(cfg, (unsigned int)®->vidcon1 + offset);
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/* set timing */
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cfg = EXYNOS_VIDTCON0_VFPD(priv->vl_vfpd - 1);
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cfg |= EXYNOS_VIDTCON0_VBPD(priv->vl_vbpd - 1);
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cfg |= EXYNOS_VIDTCON0_VSPW(priv->vl_vspw - 1);
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writel(cfg, (unsigned int)®->vidtcon0 + offset);
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cfg = EXYNOS_VIDTCON1_HFPD(priv->vl_hfpd - 1);
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cfg |= EXYNOS_VIDTCON1_HBPD(priv->vl_hbpd - 1);
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cfg |= EXYNOS_VIDTCON1_HSPW(priv->vl_hspw - 1);
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writel(cfg, (unsigned int)®->vidtcon1 + offset);
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/* set lcd size */
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cfg = EXYNOS_VIDTCON2_HOZVAL(priv->vl_col - 1) |
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EXYNOS_VIDTCON2_LINEVAL(priv->vl_row - 1) |
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EXYNOS_VIDTCON2_HOZVAL_E(priv->vl_col - 1) |
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EXYNOS_VIDTCON2_LINEVAL_E(priv->vl_row - 1);
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writel(cfg, (unsigned int)®->vidtcon2 + offset);
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}
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/* set display mode */
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cfg = readl(®->vidcon0);
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cfg &= ~EXYNOS_VIDCON0_PNRMODE_MASK;
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cfg |= (rgb_mode << EXYNOS_VIDCON0_PNRMODE_SHIFT);
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writel(cfg, ®->vidcon0);
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/* set par */
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exynos_fimd_set_par(priv, priv->win_id);
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/* set memory address */
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exynos_fimd_set_buffer_address(priv, priv->win_id, plat->base);
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/* set buffer size */
|
|
cfg = EXYNOS_VIDADDR_PAGEWIDTH(priv->vl_col *
|
|
VNBITS(priv->vl_bpix) / 8) |
|
|
EXYNOS_VIDADDR_PAGEWIDTH_E(priv->vl_col *
|
|
VNBITS(priv->vl_bpix) / 8) |
|
|
EXYNOS_VIDADDR_OFFSIZE(0) |
|
|
EXYNOS_VIDADDR_OFFSIZE_E(0);
|
|
|
|
writel(cfg, (unsigned int)®->vidw00add2 +
|
|
EXYNOS_BUFFER_SIZE(priv->win_id));
|
|
|
|
/* set clock */
|
|
exynos_fimd_set_clock(priv);
|
|
|
|
/* set rgb mode to dual lcd. */
|
|
exynos_fimd_set_dualrgb(priv, priv->dual_lcd_enabled);
|
|
|
|
/* display on */
|
|
exynos_fimd_lcd_on(priv);
|
|
|
|
/* window on */
|
|
exynos_fimd_window_on(priv, priv->win_id);
|
|
|
|
exynos_fimd_set_dp_clkcon(priv, priv->dp_enabled);
|
|
}
|
|
|
|
unsigned long exynos_fimd_calc_fbsize(struct exynos_fb_priv *priv)
|
|
{
|
|
return priv->vl_col * priv->vl_row * (VNBITS(priv->vl_bpix) / 8);
|
|
}
|
|
|
|
int exynos_fb_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct exynos_fb_priv *priv = dev_get_priv(dev);
|
|
unsigned int node = dev_of_offset(dev);
|
|
const void *blob = gd->fdt_blob;
|
|
fdt_addr_t addr;
|
|
|
|
addr = devfdt_get_addr(dev);
|
|
if (addr == FDT_ADDR_T_NONE) {
|
|
debug("Can't get the FIMD base address\n");
|
|
return -EINVAL;
|
|
}
|
|
priv->reg = (struct exynos_fb *)addr;
|
|
|
|
priv->vl_col = fdtdec_get_int(blob, node, "samsung,vl-col", 0);
|
|
if (priv->vl_col == 0) {
|
|
debug("Can't get XRES\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
priv->vl_row = fdtdec_get_int(blob, node, "samsung,vl-row", 0);
|
|
if (priv->vl_row == 0) {
|
|
debug("Can't get YRES\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
priv->vl_width = fdtdec_get_int(blob, node,
|
|
"samsung,vl-width", 0);
|
|
|
|
priv->vl_height = fdtdec_get_int(blob, node,
|
|
"samsung,vl-height", 0);
|
|
|
|
priv->vl_freq = fdtdec_get_int(blob, node, "samsung,vl-freq", 0);
|
|
if (priv->vl_freq == 0) {
|
|
debug("Can't get refresh rate\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
if (fdtdec_get_bool(blob, node, "samsung,vl-clkp"))
|
|
priv->vl_clkp = VIDEO_ACTIVE_LOW;
|
|
|
|
if (fdtdec_get_bool(blob, node, "samsung,vl-oep"))
|
|
priv->vl_oep = VIDEO_ACTIVE_LOW;
|
|
|
|
if (fdtdec_get_bool(blob, node, "samsung,vl-hsp"))
|
|
priv->vl_hsp = VIDEO_ACTIVE_LOW;
|
|
|
|
if (fdtdec_get_bool(blob, node, "samsung,vl-vsp"))
|
|
priv->vl_vsp = VIDEO_ACTIVE_LOW;
|
|
|
|
if (fdtdec_get_bool(blob, node, "samsung,vl-dp"))
|
|
priv->vl_dp = VIDEO_ACTIVE_LOW;
|
|
|
|
priv->vl_bpix = fdtdec_get_int(blob, node, "samsung,vl-bpix", 0);
|
|
if (priv->vl_bpix == 0) {
|
|
debug("Can't get bits per pixel\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
priv->vl_hspw = fdtdec_get_int(blob, node, "samsung,vl-hspw", 0);
|
|
if (priv->vl_hspw == 0) {
|
|
debug("Can't get hsync width\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
priv->vl_hfpd = fdtdec_get_int(blob, node, "samsung,vl-hfpd", 0);
|
|
if (priv->vl_hfpd == 0) {
|
|
debug("Can't get right margin\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
priv->vl_hbpd = (u_char)fdtdec_get_int(blob, node,
|
|
"samsung,vl-hbpd", 0);
|
|
if (priv->vl_hbpd == 0) {
|
|
debug("Can't get left margin\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
priv->vl_vspw = (u_char)fdtdec_get_int(blob, node,
|
|
"samsung,vl-vspw", 0);
|
|
if (priv->vl_vspw == 0) {
|
|
debug("Can't get vsync width\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
priv->vl_vfpd = fdtdec_get_int(blob, node,
|
|
"samsung,vl-vfpd", 0);
|
|
if (priv->vl_vfpd == 0) {
|
|
debug("Can't get lower margin\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
priv->vl_vbpd = fdtdec_get_int(blob, node, "samsung,vl-vbpd", 0);
|
|
if (priv->vl_vbpd == 0) {
|
|
debug("Can't get upper margin\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
priv->vl_cmd_allow_len = fdtdec_get_int(blob, node,
|
|
"samsung,vl-cmd-allow-len", 0);
|
|
|
|
priv->win_id = fdtdec_get_int(blob, node, "samsung,winid", 0);
|
|
priv->init_delay = fdtdec_get_int(blob, node,
|
|
"samsung,init-delay", 0);
|
|
priv->power_on_delay = fdtdec_get_int(blob, node,
|
|
"samsung,power-on-delay", 0);
|
|
priv->reset_delay = fdtdec_get_int(blob, node,
|
|
"samsung,reset-delay", 0);
|
|
priv->interface_mode = fdtdec_get_int(blob, node,
|
|
"samsung,interface-mode", 0);
|
|
priv->mipi_enabled = fdtdec_get_int(blob, node,
|
|
"samsung,mipi-enabled", 0);
|
|
priv->dp_enabled = fdtdec_get_int(blob, node,
|
|
"samsung,dp-enabled", 0);
|
|
priv->cs_setup = fdtdec_get_int(blob, node,
|
|
"samsung,cs-setup", 0);
|
|
priv->wr_setup = fdtdec_get_int(blob, node,
|
|
"samsung,wr-setup", 0);
|
|
priv->wr_act = fdtdec_get_int(blob, node, "samsung,wr-act", 0);
|
|
priv->wr_hold = fdtdec_get_int(blob, node, "samsung,wr-hold", 0);
|
|
|
|
priv->logo_on = fdtdec_get_int(blob, node, "samsung,logo-on", 0);
|
|
if (priv->logo_on) {
|
|
priv->logo_width = fdtdec_get_int(blob, node,
|
|
"samsung,logo-width", 0);
|
|
priv->logo_height = fdtdec_get_int(blob, node,
|
|
"samsung,logo-height", 0);
|
|
priv->logo_addr = fdtdec_get_int(blob, node,
|
|
"samsung,logo-addr", 0);
|
|
}
|
|
|
|
priv->rgb_mode = fdtdec_get_int(blob, node,
|
|
"samsung,rgb-mode", 0);
|
|
priv->pclk_name = fdtdec_get_int(blob, node,
|
|
"samsung,pclk-name", 0);
|
|
priv->sclk_div = fdtdec_get_int(blob, node,
|
|
"samsung,sclk-div", 0);
|
|
priv->dual_lcd_enabled = fdtdec_get_int(blob, node,
|
|
"samsung,dual-lcd-enabled", 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int exynos_fb_probe(struct udevice *dev)
|
|
{
|
|
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
|
|
struct exynos_fb_priv *priv = dev_get_priv(dev);
|
|
struct udevice *panel, *bridge;
|
|
struct udevice *dp;
|
|
int ret;
|
|
|
|
debug("%s: start\n", __func__);
|
|
set_system_display_ctrl();
|
|
set_lcd_clk();
|
|
|
|
#ifdef CONFIG_EXYNOS_MIPI_DSIM
|
|
exynos_init_dsim_platform_data(&panel_info);
|
|
#endif
|
|
exynos_fimd_lcd_init(dev);
|
|
|
|
ret = uclass_first_device(UCLASS_PANEL, &panel);
|
|
if (ret) {
|
|
printf("LCD panel failed to probe\n");
|
|
return ret;
|
|
}
|
|
if (!panel) {
|
|
printf("LCD panel not found\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
ret = uclass_first_device(UCLASS_DISPLAY, &dp);
|
|
if (ret) {
|
|
debug("%s: Display device error %d\n", __func__, ret);
|
|
return ret;
|
|
}
|
|
if (!dev) {
|
|
debug("%s: Display device missing\n", __func__);
|
|
return -ENODEV;
|
|
}
|
|
ret = display_enable(dp, 18, NULL);
|
|
if (ret) {
|
|
debug("%s: Display enable error %d\n", __func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
/* backlight / pwm */
|
|
ret = panel_enable_backlight(panel);
|
|
if (ret) {
|
|
debug("%s: backlight error: %d\n", __func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &bridge);
|
|
if (!ret)
|
|
ret = video_bridge_set_backlight(bridge, 80);
|
|
if (ret) {
|
|
debug("%s: No video bridge, or no backlight on bridge\n",
|
|
__func__);
|
|
exynos_pinmux_config(PERIPH_ID_PWM0, 0);
|
|
}
|
|
|
|
uc_priv->xsize = priv->vl_col;
|
|
uc_priv->ysize = priv->vl_row;
|
|
uc_priv->bpix = priv->vl_bpix;
|
|
|
|
/* Enable flushing after LCD writes if requested */
|
|
video_set_flush_dcache(dev, true);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int exynos_fb_bind(struct udevice *dev)
|
|
{
|
|
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
|
|
|
|
/* This is the maximum panel size we expect to see */
|
|
plat->size = 1920 * 1080 * 2;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct video_ops exynos_fb_ops = {
|
|
};
|
|
|
|
static const struct udevice_id exynos_fb_ids[] = {
|
|
{ .compatible = "samsung,exynos-fimd" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(exynos_fb) = {
|
|
.name = "exynos_fb",
|
|
.id = UCLASS_VIDEO,
|
|
.of_match = exynos_fb_ids,
|
|
.ops = &exynos_fb_ops,
|
|
.bind = exynos_fb_bind,
|
|
.probe = exynos_fb_probe,
|
|
.ofdata_to_platdata = exynos_fb_ofdata_to_platdata,
|
|
.priv_auto_alloc_size = sizeof(struct exynos_fb_priv),
|
|
};
|