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d9abba8254
This patch adds generic support for the Samsung s3c2440 processor. Global s3c24x0 changes to struct members converting from upper case to lower case. Signed-off-by: Craig Nauman <cnauman@diagraph.com> Cc: kevin.morfitt@fearnside-systems.co.uk Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
730 lines
11 KiB
C
730 lines
11 KiB
C
/*
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* (C) Copyright 2003
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* David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/************************************************
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* NAME : s3c24x0.h
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* Version : 31.3.2003
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*
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* common stuff for SAMSUNG S3C24X0 SoC
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************************************************/
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#ifndef __S3C24X0_H__
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#define __S3C24X0_H__
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/* Memory controller (see manual chapter 5) */
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struct s3c24x0_memctl {
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u32 bwscon;
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u32 bankcon[8];
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u32 refresh;
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u32 banksize;
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u32 mrsrb6;
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u32 mrsrb7;
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};
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/* USB HOST (see manual chapter 12) */
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struct s3c24x0_usb_host {
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u32 HcRevision;
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u32 HcControl;
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u32 HcCommonStatus;
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u32 HcInterruptStatus;
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u32 HcInterruptEnable;
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u32 HcInterruptDisable;
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u32 HcHCCA;
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u32 HcPeriodCuttendED;
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u32 HcControlHeadED;
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u32 HcControlCurrentED;
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u32 HcBulkHeadED;
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u32 HcBuldCurrentED;
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u32 HcDoneHead;
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u32 HcRmInterval;
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u32 HcFmRemaining;
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u32 HcFmNumber;
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u32 HcPeriodicStart;
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u32 HcLSThreshold;
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u32 HcRhDescriptorA;
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u32 HcRhDescriptorB;
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u32 HcRhStatus;
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u32 HcRhPortStatus1;
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u32 HcRhPortStatus2;
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};
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/* INTERRUPT (see manual chapter 14) */
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struct s3c24x0_interrupt {
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u32 srcpnd;
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u32 intmod;
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u32 intmsk;
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u32 priority;
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u32 intpnd;
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u32 intoffset;
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#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
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u32 subsrcpnd;
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u32 intsubmsk;
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#endif
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};
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/* DMAS (see manual chapter 8) */
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struct s3c24x0_dma {
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u32 disrc;
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#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
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u32 disrcc;
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#endif
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u32 didst;
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#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
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u32 didstc;
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#endif
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u32 dcon;
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u32 dstat;
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u32 dcsrc;
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u32 dcdst;
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u32 dmasktrig;
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#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) \
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|| defined(CONFIG_S3C2440)
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u32 res[1];
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#endif
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};
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struct s3c24x0_dmas {
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struct s3c24x0_dma dma[4];
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};
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/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
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/* (see S3C2410 manual chapter 7) */
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struct s3c24x0_clock_power {
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u32 locktime;
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u32 mpllcon;
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u32 upllcon;
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u32 clkcon;
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u32 clkslow;
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u32 clkdivn;
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#if defined(CONFIG_S3C2440)
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u32 camdivn;
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#endif
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};
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/* LCD CONTROLLER (see manual chapter 15) */
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struct s3c24x0_lcd {
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u32 lcdcon1;
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u32 lcdcon2;
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u32 lcdcon3;
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u32 lcdcon4;
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u32 lcdcon5;
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u32 lcdsaddr1;
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u32 lcdsaddr2;
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u32 lcdsaddr3;
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u32 redlut;
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u32 greenlut;
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u32 bluelut;
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u32 res[8];
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u32 dithmode;
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u32 tpal;
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#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
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u32 lcdintpnd;
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u32 lcdsrcpnd;
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u32 lcdintmsk;
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u32 lpcsel;
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#endif
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};
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#ifdef CONFIG_S3C2410
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/* NAND FLASH (see S3C2410 manual chapter 6) */
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struct s3c2410_nand {
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u32 nfconf;
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u32 nfcmd;
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u32 nfaddr;
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u32 nfdata;
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u32 nfstat;
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u32 nfecc;
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};
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#endif
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#ifdef CONFIG_S3C2440
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/* NAND FLASH (see S3C2440 manual chapter 6) */
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struct s3c2440_nand {
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u32 nfconf;
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u32 nfcont;
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u32 nfcmd;
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u32 nfaddr;
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u32 nfdata;
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u32 nfeccd0;
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u32 nfeccd1;
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u32 nfeccd;
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u32 nfstat;
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u32 nfstat0;
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u32 nfstat1;
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};
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#endif
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/* UART (see manual chapter 11) */
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struct s3c24x0_uart {
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u32 ulcon;
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u32 ucon;
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u32 ufcon;
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u32 umcon;
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u32 utrstat;
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u32 uerstat;
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u32 ufstat;
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u32 umstat;
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#ifdef __BIG_ENDIAN
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u8 res1[3];
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u8 utxh;
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u8 res2[3];
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u8 urxh;
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#else /* Little Endian */
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u8 utxh;
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u8 res1[3];
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u8 urxh;
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u8 res2[3];
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#endif
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u32 ubrdiv;
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};
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/* PWM TIMER (see manual chapter 10) */
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struct s3c24x0_timer {
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u32 tcntb;
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u32 tcmpb;
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u32 tcnto;
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};
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struct s3c24x0_timers {
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u32 tcfg0;
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u32 tcfg1;
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u32 tcon;
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struct s3c24x0_timer ch[4];
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u32 tcntb4;
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u32 tcnto4;
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};
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/* USB DEVICE (see manual chapter 13) */
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struct s3c24x0_usb_dev_fifos {
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#ifdef __BIG_ENDIAN
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u8 res[3];
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u8 ep_fifo_reg;
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#else /* little endian */
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u8 ep_fifo_reg;
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u8 res[3];
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#endif
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};
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struct s3c24x0_usb_dev_dmas {
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#ifdef __BIG_ENDIAN
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u8 res1[3];
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u8 ep_dma_con;
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u8 res2[3];
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u8 ep_dma_unit;
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u8 res3[3];
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u8 ep_dma_fifo;
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u8 res4[3];
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u8 ep_dma_ttc_l;
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u8 res5[3];
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u8 ep_dma_ttc_m;
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u8 res6[3];
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u8 ep_dma_ttc_h;
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#else /* little endian */
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u8 ep_dma_con;
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u8 res1[3];
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u8 ep_dma_unit;
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u8 res2[3];
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u8 ep_dma_fifo;
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u8 res3[3];
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u8 ep_dma_ttc_l;
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u8 res4[3];
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u8 ep_dma_ttc_m;
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u8 res5[3];
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u8 ep_dma_ttc_h;
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u8 res6[3];
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#endif
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};
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struct s3c24x0_usb_device {
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#ifdef __BIG_ENDIAN
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u8 res1[3];
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u8 func_addr_reg;
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u8 res2[3];
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u8 pwr_reg;
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u8 res3[3];
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u8 ep_int_reg;
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u8 res4[15];
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u8 usb_int_reg;
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u8 res5[3];
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u8 ep_int_en_reg;
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u8 res6[15];
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u8 usb_int_en_reg;
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u8 res7[3];
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u8 frame_num1_reg;
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u8 res8[3];
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u8 frame_num2_reg;
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u8 res9[3];
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u8 index_reg;
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u8 res10[7];
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u8 maxp_reg;
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u8 res11[3];
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u8 ep0_csr_in_csr1_reg;
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u8 res12[3];
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u8 in_csr2_reg;
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u8 res13[7];
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u8 out_csr1_reg;
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u8 res14[3];
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u8 out_csr2_reg;
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u8 res15[3];
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u8 out_fifo_cnt1_reg;
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u8 res16[3];
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u8 out_fifo_cnt2_reg;
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#else /* little endian */
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u8 func_addr_reg;
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u8 res1[3];
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u8 pwr_reg;
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u8 res2[3];
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u8 ep_int_reg;
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u8 res3[15];
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u8 usb_int_reg;
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u8 res4[3];
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u8 ep_int_en_reg;
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u8 res5[15];
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u8 usb_int_en_reg;
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u8 res6[3];
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u8 frame_num1_reg;
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u8 res7[3];
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u8 frame_num2_reg;
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u8 res8[3];
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u8 index_reg;
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u8 res9[7];
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u8 maxp_reg;
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u8 res10[7];
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u8 ep0_csr_in_csr1_reg;
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u8 res11[3];
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u8 in_csr2_reg;
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u8 res12[3];
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u8 out_csr1_reg;
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u8 res13[7];
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u8 out_csr2_reg;
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u8 res14[3];
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u8 out_fifo_cnt1_reg;
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u8 res15[3];
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u8 out_fifo_cnt2_reg;
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u8 res16[3];
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#endif /* __BIG_ENDIAN */
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struct s3c24x0_usb_dev_fifos fifo[5];
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struct s3c24x0_usb_dev_dmas dma[5];
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};
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/* WATCH DOG TIMER (see manual chapter 18) */
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struct s3c24x0_watchdog {
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u32 wtcon;
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u32 wtdat;
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u32 wtcnt;
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};
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/* IIC (see manual chapter 20) */
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struct s3c24x0_i2c {
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u32 iiccon;
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u32 iicstat;
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u32 iicadd;
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u32 iicds;
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};
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/* IIS (see manual chapter 21) */
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struct s3c24x0_i2s {
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#ifdef __BIG_ENDIAN
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u16 res1;
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u16 iiscon;
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u16 res2;
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u16 iismod;
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u16 res3;
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u16 iispsr;
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u16 res4;
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u16 iisfcon;
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u16 res5;
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u16 iisfifo;
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#else /* little endian */
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u16 iiscon;
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u16 res1;
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u16 iismod;
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u16 res2;
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u16 iispsr;
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u16 res3;
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u16 iisfcon;
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u16 res4;
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u16 iisfifo;
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u16 res5;
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#endif
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};
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/* I/O PORT (see manual chapter 9) */
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struct s3c24x0_gpio {
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#ifdef CONFIG_S3C2400
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u32 pacon;
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u32 padat;
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u32 pbcon;
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u32 pbdat;
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u32 pbup;
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u32 pccon;
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u32 pcdat;
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u32 pcup;
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u32 pdcon;
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u32 pddat;
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u32 pdup;
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u32 pecon;
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u32 pedat;
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u32 peup;
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u32 pfcon;
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u32 pfdat;
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u32 pfup;
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u32 pgcon;
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u32 pgdat;
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u32 pgup;
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u32 opencr;
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u32 misccr;
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u32 extint;
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#endif
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#ifdef CONFIG_S3C2410
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u32 gpacon;
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u32 gpadat;
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u32 res1[2];
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u32 gpbcon;
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u32 gpbdat;
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u32 gpbup;
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u32 res2;
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u32 gpccon;
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u32 gpcdat;
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u32 gpcup;
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u32 res3;
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u32 gpdcon;
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u32 gpddat;
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u32 gpdup;
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u32 res4;
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u32 gpecon;
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u32 gpedat;
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u32 gpeup;
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u32 res5;
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u32 gpfcon;
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u32 gpfdat;
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u32 gpfup;
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u32 res6;
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u32 gpgcon;
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u32 gpgdat;
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u32 gpgup;
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u32 res7;
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u32 gphcon;
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u32 gphdat;
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u32 gphup;
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u32 res8;
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u32 misccr;
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u32 dclkcon;
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u32 extint0;
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u32 extint1;
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u32 extint2;
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u32 eintflt0;
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u32 eintflt1;
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u32 eintflt2;
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u32 eintflt3;
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u32 eintmask;
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u32 eintpend;
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u32 gstatus0;
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u32 gstatus1;
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u32 gstatus2;
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u32 gstatus3;
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u32 gstatus4;
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#endif
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#if defined(CONFIG_S3C2440)
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u32 gpacon;
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u32 gpadat;
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u32 res1[2];
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u32 gpbcon;
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u32 gpbdat;
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u32 gpbup;
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u32 res2;
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u32 gpccon;
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u32 gpcdat;
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u32 gpcup;
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u32 res3;
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u32 gpdcon;
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u32 gpddat;
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u32 gpdup;
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u32 res4;
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u32 gpecon;
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u32 gpedat;
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u32 gpeup;
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u32 res5;
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u32 gpfcon;
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u32 gpfdat;
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u32 gpfup;
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u32 res6;
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u32 gpgcon;
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u32 gpgdat;
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u32 gpgup;
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u32 res7;
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u32 gphcon;
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u32 gphdat;
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u32 gphup;
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u32 res8;
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u32 misccr;
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u32 dclkcon;
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u32 extint0;
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u32 extint1;
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u32 extint2;
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u32 eintflt0;
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u32 eintflt1;
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u32 eintflt2;
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u32 eintflt3;
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u32 eintmask;
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u32 eintpend;
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u32 gstatus0;
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u32 gstatus1;
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u32 gstatus2;
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u32 gstatus3;
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u32 gstatus4;
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u32 res9;
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u32 dsc0;
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u32 dsc1;
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u32 mslcon;
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u32 gpjcon;
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u32 gpjdat;
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u32 gpjup;
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u32 res10;
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#endif
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};
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/* RTC (see manual chapter 17) */
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struct s3c24x0_rtc {
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#ifdef __BIG_ENDIAN
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u8 res1[67];
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u8 rtccon;
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u8 res2[3];
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u8 ticnt;
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u8 res3[11];
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u8 rtcalm;
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u8 res4[3];
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u8 almsec;
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u8 res5[3];
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u8 almmin;
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u8 res6[3];
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u8 almhour;
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u8 res7[3];
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u8 almdate;
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u8 res8[3];
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u8 almmon;
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u8 res9[3];
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u8 almyear;
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u8 res10[3];
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u8 rtcrst;
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u8 res11[3];
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u8 bcdsec;
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u8 res12[3];
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u8 bcdmin;
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u8 res13[3];
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u8 bcdhour;
|
|
u8 res14[3];
|
|
u8 bcddate;
|
|
u8 res15[3];
|
|
u8 bcdday;
|
|
u8 res16[3];
|
|
u8 bcdmon;
|
|
u8 res17[3];
|
|
u8 bcdyear;
|
|
#else /* little endian */
|
|
u8 res0[64];
|
|
u8 rtccon;
|
|
u8 res1[3];
|
|
u8 ticnt;
|
|
u8 res2[11];
|
|
u8 rtcalm;
|
|
u8 res3[3];
|
|
u8 almsec;
|
|
u8 res4[3];
|
|
u8 almmin;
|
|
u8 res5[3];
|
|
u8 almhour;
|
|
u8 res6[3];
|
|
u8 almdate;
|
|
u8 res7[3];
|
|
u8 almmon;
|
|
u8 res8[3];
|
|
u8 almyear;
|
|
u8 res9[3];
|
|
u8 rtcrst;
|
|
u8 res10[3];
|
|
u8 bcdsec;
|
|
u8 res11[3];
|
|
u8 bcdmin;
|
|
u8 res12[3];
|
|
u8 bcdhour;
|
|
u8 res13[3];
|
|
u8 bcddate;
|
|
u8 res14[3];
|
|
u8 bcdday;
|
|
u8 res15[3];
|
|
u8 bcdmon;
|
|
u8 res16[3];
|
|
u8 bcdyear;
|
|
u8 res17[3];
|
|
#endif
|
|
};
|
|
|
|
|
|
/* ADC (see manual chapter 16) */
|
|
struct s3c2400_adc {
|
|
u32 adccon;
|
|
u32 adcdat;
|
|
};
|
|
|
|
|
|
/* ADC (see manual chapter 16) */
|
|
struct s3c2410_adc {
|
|
u32 adccon;
|
|
u32 adctsc;
|
|
u32 adcdly;
|
|
u32 adcdat0;
|
|
u32 adcdat1;
|
|
};
|
|
|
|
|
|
/* SPI (see manual chapter 22) */
|
|
struct s3c24x0_spi_channel {
|
|
u8 spcon;
|
|
u8 res1[3];
|
|
u8 spsta;
|
|
u8 res2[3];
|
|
u8 sppin;
|
|
u8 res3[3];
|
|
u8 sppre;
|
|
u8 res4[3];
|
|
u8 sptdat;
|
|
u8 res5[3];
|
|
u8 sprdat;
|
|
u8 res6[3];
|
|
u8 res7[16];
|
|
};
|
|
|
|
struct s3c24x0_spi {
|
|
struct s3c24x0_spi_channel ch[S3C24X0_SPI_CHANNELS];
|
|
};
|
|
|
|
|
|
/* MMC INTERFACE (see S3C2400 manual chapter 19) */
|
|
struct s3c2400_mmc {
|
|
#ifdef __BIG_ENDIAN
|
|
u8 res1[3];
|
|
u8 mmcon;
|
|
u8 res2[3];
|
|
u8 mmcrr;
|
|
u8 res3[3];
|
|
u8 mmfcon;
|
|
u8 res4[3];
|
|
u8 mmsta;
|
|
u16 res5;
|
|
u16 mmfsta;
|
|
u8 res6[3];
|
|
u8 mmpre;
|
|
u16 res7;
|
|
u16 mmlen;
|
|
u8 res8[3];
|
|
u8 mmcr7;
|
|
u32 mmrsp[4];
|
|
u8 res9[3];
|
|
u8 mmcmd0;
|
|
u32 mmcmd1;
|
|
u16 res10;
|
|
u16 mmcr16;
|
|
u8 res11[3];
|
|
u8 mmdat;
|
|
#else
|
|
u8 mmcon;
|
|
u8 res1[3];
|
|
u8 mmcrr;
|
|
u8 res2[3];
|
|
u8 mmfcon;
|
|
u8 res3[3];
|
|
u8 mmsta;
|
|
u8 res4[3];
|
|
u16 mmfsta;
|
|
u16 res5;
|
|
u8 mmpre;
|
|
u8 res6[3];
|
|
u16 mmlen;
|
|
u16 res7;
|
|
u8 mmcr7;
|
|
u8 res8[3];
|
|
u32 mmrsp[4];
|
|
u8 mmcmd0;
|
|
u8 res9[3];
|
|
u32 mmcmd1;
|
|
u16 mmcr16;
|
|
u16 res10;
|
|
u8 mmdat;
|
|
u8 res11[3];
|
|
#endif
|
|
};
|
|
|
|
|
|
/* SD INTERFACE (see S3C2410 manual chapter 19) */
|
|
struct s3c2410_sdi {
|
|
u32 sdicon;
|
|
u32 sdipre;
|
|
u32 sdicarg;
|
|
u32 sdiccon;
|
|
u32 sdicsta;
|
|
u32 sdirsp0;
|
|
u32 sdirsp1;
|
|
u32 sdirsp2;
|
|
u32 sdirsp3;
|
|
u32 sdidtimer;
|
|
u32 sdibsize;
|
|
u32 sdidcon;
|
|
u32 sdidcnt;
|
|
u32 sdidsta;
|
|
u32 sdifsta;
|
|
#ifdef __BIG_ENDIAN
|
|
u8 res[3];
|
|
u8 sdidat;
|
|
#else
|
|
u8 sdidat;
|
|
u8 res[3];
|
|
#endif
|
|
u32 sdiimsk;
|
|
};
|
|
|
|
#endif /*__S3C24X0_H__*/
|