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https://github.com/AsahiLinux/u-boot
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4788704dd8
Add ethernet nodes for Serval SoCs family. There are 2 pcb in this family: pcb105 and pcb106. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
207 lines
4.4 KiB
Text
207 lines
4.4 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mscc,serval";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "mips,mips24KEc";
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device_type = "cpu";
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clocks = <&cpu_clk>;
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reg = <0>;
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};
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};
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aliases {
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serial0 = &uart0;
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};
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cpuintc: interrupt-controller@0 {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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cpu_clk: cpu-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <416666666>;
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};
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sys_clk: sys-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <208333333>;
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};
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ahb_clk: ahb-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <208333333>;
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x70000000 0x2000000>;
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interrupt-parent = <&intc>;
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cpu_ctrl: syscon@0 {
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compatible = "mscc,serval-cpu-syscon", "syscon";
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reg = <0x0 0x2c>;
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};
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intc: interrupt-controller@70 {
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compatible = "mscc,serval-icpu-intr";
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reg = <0x70 0x70>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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};
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uart0: serial@100000 {
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pinctrl-0 = <&uart_pins>;
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pinctrl-names = "default";
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compatible = "ns16550a";
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reg = <0x100000 0x20>;
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interrupts = <6>;
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clocks = <&ahb_clk>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart2: serial@100800 {
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pinctrl-0 = <&uart2_pins>;
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pinctrl-names = "default";
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compatible = "ns16550a";
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reg = <0x100800 0x20>;
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interrupts = <7>;
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clocks = <&ahb_clk>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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reset@1070008 {
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compatible = "mscc,serval-chip-reset";
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reg = <0x1070008 0x4>;
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};
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gpio: pinctrl@1070034 {
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compatible = "mscc,serval-pinctrl";
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reg = <0x1070034 0x68>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&gpio 0 0 22>;
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sgpio_pins: sgpio-pins {
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pins = "GPIO_0", "GPIO_2", "GPIO_3", "GPIO_1";
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function = "sio";
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};
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uart_pins: uart-pins {
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pins = "GPIO_26", "GPIO_27";
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function = "uart";
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};
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uart2_pins: uart2-pins {
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pins = "GPIO_13", "GPIO_14";
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function = "uart2";
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};
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};
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spi0: spi-bitbang {
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compatible = "mscc,luton-bb-spi";
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status = "okay";
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reg = <0x50 0x4>;
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num-chipselects = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sgpio: gpio@10700b4 {
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compatible = "mscc,luton-sgpio";
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status = "disabled";
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clocks = <&sys_clk>;
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pinctrl-0 = <&sgpio_pins>;
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pinctrl-names = "default";
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reg = <0x10700b4 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&sgpio 0 0 64>;
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};
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switch: switch@011e0000 {
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compatible = "mscc,vsc7418-switch";
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reg = <0x011e0000 0x0100>, // VTSS_TO_DEV0
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<0x011f0000 0x0100>, // VTSS_TO_DEV1
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<0x01200000 0x0100>, // VTSS_TO_DEV2
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<0x01210000 0x0100>, // VTSS_TO_DEV3
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<0x01220000 0x0100>, // VTSS_TO_DEV4
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<0x01230000 0x0100>, // VTSS_TO_DEV5
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<0x01240000 0x0100>, // VTSS_TO_DEV6
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<0x01250000 0x0100>, // VTSS_TO_DEV7
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<0x01260000 0x0100>, // VTSS_TO_DEV8
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<0x01270000 0x0100>, // VTSS_TO_DEV9
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<0x01280000 0x0100>, // VTSS_TO_DEV10
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<0x01900000 0x100000>, // ANA
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<0x01080000 0x20000>, // QS
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<0x01800000 0x100000>, // QSYS
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<0x01030000 0x10000>, // REW
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<0x01010000 0x20000>, // SYS
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<0x010a0000 0x10000>; // HSIO
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reg-names = "port0", "port1", "port2", "port3",
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"port4", "port5", "port6", "port7",
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"port8", "port9", "port10",
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"ana", "qs", "qsys", "rew", "sys",
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"hsio";
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status = "okay";
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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mdio0: mdio@0107005c {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mscc,serval-miim";
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reg = <0x0107005c 0x24>;
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status = "disabled";
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};
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mdio1: mdio@01070080 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mscc,serval-miim";
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reg = <0x01070080 0x24>;
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status = "disabled";
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};
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hsio: syscon@10d0000 {
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compatible = "mscc,serval-hsio", "syscon", "simple-mfd";
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reg = <0x10a0000 0x10000>;
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serdes_hsio: serdes_hsio {
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compatible = "mscc,vsc7418-serdes";
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#phy-cells = <3>;
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};
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};
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};
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};
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