mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-29 19:02:12 +00:00
6cc04547cb
Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
439 lines
10 KiB
C
439 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Traverse Ten64 Family board
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* Copyright 2017-2018 NXP
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* Copyright 2019-2021 Traverse Technologies
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*/
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#include <common.h>
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#include <display_options.h>
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#include <dm/uclass.h>
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#include <env.h>
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#include <i2c.h>
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#include <init.h>
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#include <log.h>
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#include <malloc.h>
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#include <errno.h>
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#include <misc.h>
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#include <netdev.h>
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#include <fsl_ifc.h>
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#include <fsl_ddr.h>
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#include <fsl_sec.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <fdt_support.h>
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#include <linux/delay.h>
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#include <linux/libfdt.h>
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#include <fsl-mc/fsl_mc.h>
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#include <env_internal.h>
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#include <asm/arch-fsl-layerscape/soc.h>
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#include <asm/arch/ppa.h>
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#include <hwconfig.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/soc.h>
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#include <asm/arch-fsl-layerscape/fsl_icid.h>
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#include <fsl_immap.h>
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#include "../common/ten64-controller.h"
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#define I2C_RETIMER_ADDR 0x27
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DECLARE_GLOBAL_DATA_PTR;
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static int ten64_read_board_info(struct t64uc_board_info *);
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static void ten64_set_macaddrs_from_board_info(struct t64uc_board_info *);
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static void ten64_board_retimer_ds110df410_init(void);
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enum {
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TEN64_BOARD_REV_A = 0xFF,
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TEN64_BOARD_REV_B = 0xFE,
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TEN64_BOARD_REV_C = 0xFD
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};
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#define RESV_MEM_IN_BANK(b) (gd->arch.resv_ram >= base[b] && \
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gd->arch.resv_ram < base[b] + size[b])
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int board_early_init_f(void)
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{
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fsl_lsch3_early_init_f();
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return 0;
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}
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static u32 ten64_get_board_rev(void)
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{
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struct ccsr_gur *dcfg = (void *)CFG_SYS_FSL_GUTS_ADDR;
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u32 board_rev_in = in_le32(&dcfg->gpporcr1);
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return board_rev_in;
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}
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int checkboard(void)
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{
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enum boot_src src = get_boot_src();
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char boardmodel[32];
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struct t64uc_board_info boardinfo;
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u32 board_rev = ten64_get_board_rev();
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switch (board_rev) {
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case TEN64_BOARD_REV_A:
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snprintf(boardmodel, 32, "1064-0201A (Alpha)");
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break;
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case TEN64_BOARD_REV_B:
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snprintf(boardmodel, 32, "1064-0201B (Beta)");
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break;
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case TEN64_BOARD_REV_C:
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snprintf(boardmodel, 32, "1064-0201C");
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break;
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default:
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snprintf(boardmodel, 32, "1064 Revision %X", (0xFF - board_rev));
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break;
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}
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printf("Board: %s, boot from ", boardmodel);
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if (src == BOOT_SOURCE_SD_MMC)
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puts("SD card\n");
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else if (src == BOOT_SOURCE_QSPI_NOR)
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puts("QSPI\n");
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else
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printf("Unknown boot source %d\n", src);
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puts("Controller: ");
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if (CONFIG_IS_ENABLED(TEN64_CONTROLLER)) {
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/* Driver not compatible with alpha/beta board MCU firmware */
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if (board_rev <= TEN64_BOARD_REV_C) {
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if (ten64_read_board_info(&boardinfo)) {
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puts("ERROR: unable to communicate\n");
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} else {
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printf("firmware %d.%d.%d\n",
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boardinfo.fwversion_major,
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boardinfo.fwversion_minor,
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boardinfo.fwversion_patch);
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ten64_set_macaddrs_from_board_info(&boardinfo);
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}
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} else {
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puts("not supported on this board revision\n");
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}
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} else {
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puts("driver not enabled (no MAC addresses or other information will be read)\n");
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}
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return 0;
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}
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int board_init(void)
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{
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init_final_memctl_regs();
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if (CONFIG_IS_ENABLED(FSL_CAAM))
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sec_init();
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return 0;
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}
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int fsl_initdram(void)
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{
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gd->ram_size = tfa_get_dram_size();
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if (!gd->ram_size)
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gd->ram_size = fsl_ddr_sdram_size();
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return 0;
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}
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void detail_board_ddr_info(void)
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{
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puts("\nDDR ");
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print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
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print_ddr_info(0);
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}
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void board_quiesce_devices(void)
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{
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if (IS_ENABLED(CONFIG_FSL_MC_ENET))
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fsl_mc_ldpaa_exit(gd->bd);
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}
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void fdt_fixup_board_enet(void *fdt)
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{
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int offset;
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offset = fdt_path_offset(fdt, "/fsl-mc");
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if (offset < 0)
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offset = fdt_path_offset(fdt, "/soc/fsl-mc");
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if (offset < 0) {
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printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
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__func__, offset);
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return;
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}
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if (get_mc_boot_status() == 0 &&
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(is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
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fdt_status_okay(fdt, offset);
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else
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fdt_status_fail(fdt, offset);
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}
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/* Called after SoC board_late_init in fsl-layerscape/soc.c */
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int fsl_board_late_init(void)
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{
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ten64_board_retimer_ds110df410_init();
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return 0;
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}
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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int i;
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u16 mc_memory_bank = 0;
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u64 *base;
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u64 *size;
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u64 mc_memory_base = 0;
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u64 mc_memory_size = 0;
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u16 total_memory_banks;
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debug("%s blob=0x%p\n", __func__, blob);
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ft_cpu_setup(blob, bd);
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fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
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if (mc_memory_base != 0)
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mc_memory_bank++;
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total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
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base = calloc(total_memory_banks, sizeof(u64));
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size = calloc(total_memory_banks, sizeof(u64));
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/* fixup DT for the two GPP DDR banks */
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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base[i] = gd->bd->bi_dram[i].start;
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size[i] = gd->bd->bi_dram[i].size;
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/* reduce size if reserved memory is within this bank */
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if (CONFIG_IS_ENABLED(RESV_RAM) && RESV_MEM_IN_BANK(i))
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size[i] = gd->arch.resv_ram - base[i];
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}
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if (mc_memory_base != 0) {
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for (i = 0; i <= total_memory_banks; i++) {
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if (base[i] == 0 && size[i] == 0) {
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base[i] = mc_memory_base;
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size[i] = mc_memory_size;
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break;
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}
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}
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}
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fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
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fdt_fsl_mc_fixup_iommu_map_entry(blob);
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if (CONFIG_IS_ENABLED(FSL_MC_ENET))
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fdt_fixup_board_enet(blob);
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fdt_fixup_icid(blob);
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return 0;
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}
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#define MACADDRBITS(a, b) (u8)(((a) >> (b)) & 0xFF)
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/** Probe and return a udevice for the Ten64 board microcontroller.
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* Optionally, return the I2C bus the microcontroller resides on
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* @i2c_bus_out: return I2C bus device handle in this pointer
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*/
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static int ten64_get_micro_udevice(struct udevice **ucdev, struct udevice **i2c_bus_out)
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{
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int ret;
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struct udevice *i2cbus;
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ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &i2cbus);
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if (ret) {
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printf("%s: Could not get I2C UCLASS", __func__);
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return ret;
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}
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if (i2c_bus_out)
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*i2c_bus_out = i2cbus;
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ret = dm_i2c_probe(i2cbus, 0x7E, DM_I2C_CHIP_RD_ADDRESS, ucdev);
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if (ret) {
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printf("%s: Could not get microcontroller device\n", __func__);
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return ret;
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}
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return ret;
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}
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static int ten64_read_board_info(struct t64uc_board_info *boardinfo)
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{
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struct udevice *ucdev;
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int ret;
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ret = ten64_get_micro_udevice(&ucdev, NULL);
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if (ret)
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return ret;
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ret = misc_call(ucdev, TEN64_CNTRL_GET_BOARD_INFO, NULL, 0, (void *)boardinfo, 0);
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if (ret)
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return ret;
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return 0;
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}
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static void ten64_set_macaddrs_from_board_info(struct t64uc_board_info *boardinfo)
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{
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char ethaddr[18];
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char enetvar[10];
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u8 intfidx, this_dpmac_num;
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u64 macaddr = 0;
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/* We will copy the MAC address returned from the
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* uC (48 bits) into the u64 macaddr
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*/
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u8 *macaddr_bytes = (u8 *)&macaddr + 2;
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/** MAC addresses are allocated in order of the physical port numbers,
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* DPMAC7->10 is "eth0" through "eth3"
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* DPMAC3->6 is "eth4" through "eth7"
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* DPMAC2 and 1 are "eth8" and "eth9" respectively
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*/
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int allocation_order[10] = {7, 8, 9, 10, 3, 4, 5, 6, 2, 1};
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memcpy(macaddr_bytes, boardinfo->mac, 6);
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/* MAC address bytes from uC are in big endian,
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* convert to CPU
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*/
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macaddr = __be64_to_cpu(macaddr);
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for (intfidx = 0; intfidx < 10; intfidx++) {
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snprintf(ethaddr, 18, "%02X:%02X:%02X:%02X:%02X:%02X",
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MACADDRBITS(macaddr, 40),
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MACADDRBITS(macaddr, 32),
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MACADDRBITS(macaddr, 24),
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MACADDRBITS(macaddr, 16),
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MACADDRBITS(macaddr, 8),
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MACADDRBITS(macaddr, 0));
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this_dpmac_num = allocation_order[intfidx];
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printf("DPMAC%d: %s\n", this_dpmac_num, ethaddr);
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snprintf(enetvar, 10,
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(this_dpmac_num != 1) ? "eth%daddr" : "ethaddr",
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this_dpmac_num - 1);
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macaddr++;
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if (!env_get(enetvar))
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env_set(enetvar, ethaddr);
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}
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}
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/* The retimer (DS110DF410) is one of the devices without
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* a RESET line, but a power switch is on the board
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* allowing it to be reset via uC command
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*/
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static int board_cycle_retimer(struct udevice **retim_dev)
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{
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int ret;
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u8 loop;
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struct udevice *uc_dev;
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struct udevice *i2cbus;
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ret = ten64_get_micro_udevice(&uc_dev, &i2cbus);
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if (ret)
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return ret;
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ret = dm_i2c_probe(i2cbus, I2C_RETIMER_ADDR, 0, retim_dev);
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if (ret == 0) {
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puts("(retimer on, resetting...) ");
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ret = misc_call(uc_dev, TEN64_CNTRL_10G_OFF, NULL, 0, NULL, 0);
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mdelay(1000);
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}
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ret = misc_call(uc_dev, TEN64_CNTRL_10G_ON, NULL, 0, NULL, 0);
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// Wait for retimer to come back
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for (loop = 0; loop < 5; loop++) {
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ret = dm_i2c_probe(i2cbus, I2C_RETIMER_ADDR, 0, retim_dev);
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if (ret == 0)
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return 0;
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mdelay(500);
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}
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return -ENOSYS;
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}
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/* ten64_board_retimer_ds110df410_init() - Configure the 10G retimer
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* Adopted from the t102xqds board file
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*/
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static void ten64_board_retimer_ds110df410_init(void)
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{
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u8 reg;
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int ret;
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struct udevice *retim_dev;
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u32 board_rev = ten64_get_board_rev();
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puts("Retimer: ");
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/* Retimer power cycle not implemented on early board
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* revisions/controller firmwares
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*/
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if (CONFIG_IS_ENABLED(TEN64_CONTROLLER) &&
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board_rev >= TEN64_BOARD_REV_C) {
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ret = board_cycle_retimer(&retim_dev);
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if (ret) {
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puts("Retimer power on failed\n");
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return;
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}
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}
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/* Access to Control/Shared register */
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reg = 0x0;
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ret = dm_i2c_write(retim_dev, 0xff, ®, 1);
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if (ret) {
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printf("Error writing to retimer register (error %d)\n", ret);
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return;
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}
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/* Read device revision and ID */
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dm_i2c_read(retim_dev, 1, ®, 1);
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if (reg == 0xF0)
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puts("DS110DF410 found\n");
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else
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printf("Unknown retimer 0x%xn\n", reg);
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/* Enable Broadcast */
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reg = 0x0c;
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dm_i2c_write(retim_dev, 0xff, ®, 1);
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/* Perform a full reset (state, channel and clock)
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* for all channels
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* as the DS110DF410 does not have a RESET line
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*/
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dm_i2c_read(retim_dev, 0, ®, 1);
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reg |= 0x7;
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dm_i2c_write(retim_dev, 0, ®, 1);
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/* Set rate/subrate = 0 */
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reg = 0x6;
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dm_i2c_write(retim_dev, 0x2F, ®, 1);
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/* Set data rate as 10.3125 Gbps */
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reg = 0x0;
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dm_i2c_write(retim_dev, 0x60, ®, 1);
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reg = 0xb2;
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dm_i2c_write(retim_dev, 0x61, ®, 1);
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reg = 0x90;
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dm_i2c_write(retim_dev, 0x62, ®, 1);
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reg = 0xb3;
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dm_i2c_write(retim_dev, 0x63, ®, 1);
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reg = 0xff;
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dm_i2c_write(retim_dev, 0x64, ®, 1);
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/* Invert channel 2 (Lower SFP TX to CPU) due to the SFP being inverted */
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reg = 0x05;
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dm_i2c_write(retim_dev, 0xFF, ®, 1);
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dm_i2c_read(retim_dev, 0x1F, ®, 1);
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reg |= 0x80;
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dm_i2c_write(retim_dev, 0x1F, ®, 1);
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puts("OK\n");
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}
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