mirror of
https://github.com/AsahiLinux/u-boot
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30426492d3
J721e SoM as a 64MB HyperFlash on board. Add pinmux and DT node for the same. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
445 lines
12 KiB
Text
445 lines
12 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
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*/
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/dts-v1/;
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#include "k3-j721e-som-p0.dtsi"
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#include "k3-j721e-ddr-evm-lp4-4266.dtsi"
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#include "k3-j721e-ddr.dtsi"
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#include <dt-bindings/phy/phy-cadence.h>
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/ {
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aliases {
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remoteproc0 = &sysctrler;
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remoteproc1 = &a72_0;
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};
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chosen {
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stdout-path = "serial2:115200n8";
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tick-timer = &timer1;
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};
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a72_0: a72@0 {
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compatible = "ti,am654-rproc";
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reg = <0x0 0x00a90000 0x0 0x10>;
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power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
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<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
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resets = <&k3_reset 202 0>;
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clocks = <&k3_clks 61 1>;
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assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
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assigned-clock-rates = <2000000000>, <200000000>;
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ti,sci = <&dmsc>;
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ti,sci-proc-id = <32>;
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ti,sci-host-id = <10>;
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u-boot,dm-spl;
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};
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clk_200mhz: dummy_clock_200mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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u-boot,dm-spl;
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};
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clk_19_2mhz: dummy_clock_19_2mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <19200000>;
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u-boot,dm-spl;
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};
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};
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&cbass_mcu_wakeup {
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mcu_secproxy: secproxy@28380000 {
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u-boot,dm-spl;
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compatible = "ti,am654-secure-proxy";
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reg = <0x0 0x2a380000 0x0 0x80000>,
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<0x0 0x2a400000 0x0 0x80000>,
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<0x0 0x2a480000 0x0 0x80000>;
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reg-names = "rt", "scfg", "target_data";
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#mbox-cells = <1>;
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};
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sysctrler: sysctrler {
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u-boot,dm-spl;
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compatible = "ti,am654-system-controller";
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mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
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mbox-names = "tx", "rx";
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};
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wkup_vtm0: wkup_vtm@42040000 {
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compatible = "ti,am654-vtm", "ti,j721e-avs";
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reg = <0x0 0x42040000 0x0 0x330>;
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power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
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#thermal-sensor-cells = <1>;
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};
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dm_tifs: dm-tifs {
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compatible = "ti,j721e-dm-sci";
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ti,host-id = <3>;
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ti,secure-host;
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mbox-names = "rx", "tx";
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mboxes= <&mcu_secproxy 21>,
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<&mcu_secproxy 23>;
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u-boot,dm-spl;
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};
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};
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&cbass_main {
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main_esm: esm@700000 {
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compatible = "ti,j721e-esm";
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reg = <0x0 0x700000 0x0 0x1000>;
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ti,esm-pins = <344>, <345>;
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u-boot,dm-spl;
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};
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};
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&dmsc {
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mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
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mbox-names = "tx", "rx", "notify";
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ti,host-id = <4>;
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ti,secure-host;
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};
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&wkup_pmx0 {
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wkup_uart0_pins_default: wkup_uart0_pins_default {
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u-boot,dm-spl;
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
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J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
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>;
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};
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mcu_uart0_pins_default: mcu_uart0_pins_default {
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u-boot,dm-spl;
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */
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J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */
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J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
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J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
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>;
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};
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wkup_i2c0_pins_default: wkup-i2c0-pins-default {
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
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J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
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>;
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};
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mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
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J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
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J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
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J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
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J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
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J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
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J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
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J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
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J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
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J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
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J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
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J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
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J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
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J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
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>;
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};
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wkup_gpio_pins_default: wkup-gpio-pins-default {
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* WKUP_GPIO0_8 */
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>;
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};
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mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
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J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */
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J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */
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J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */
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J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */
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J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */
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J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */
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J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */
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J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */
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J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */
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J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
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>;
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};
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mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
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u-boot,dm-spl;
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
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J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */
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J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */
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J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */
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J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */
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J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
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J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
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J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
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>;
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};
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};
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&main_pmx0 {
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main_uart0_pins_default: main_uart0_pins_default {
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u-boot,dm-spl;
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pinctrl-single,pins = <
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J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */
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J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */
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J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
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J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
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>;
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};
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main_usbss0_pins_default: main_usbss0_pins_default {
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pinctrl-single,pins = <
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J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
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J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
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>;
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};
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main_mmc1_pins_default: main_mmc1_pins_default {
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pinctrl-single,pins = <
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J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
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J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
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J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
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J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
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J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
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J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
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J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
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J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
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J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
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>;
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};
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main_i2c0_pins_default: main-i2c0-pins-default {
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pinctrl-single,pins = <
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J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
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J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
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>;
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};
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};
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&wkup_uart0 {
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u-boot,dm-spl;
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pinctrl-names = "default";
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pinctrl-0 = <&wkup_uart0_pins_default>;
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status = "okay";
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};
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&wkup_gpio0 {
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pinctrl-names = "default";
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pinctrl-0 = <&wkup_gpio_pins_default>;
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};
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&mcu_uart0 {
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/delete-property/ power-domains;
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/delete-property/ clocks;
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/delete-property/ clock-names;
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pinctrl-names = "default";
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pinctrl-0 = <&mcu_uart0_pins_default>;
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status = "okay";
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clock-frequency = <48000000>;
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};
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&main_uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_uart0_pins_default>;
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status = "okay";
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power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
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};
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&main_sdhci0 {
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/delete-property/ power-domains;
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/delete-property/ assigned-clocks;
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/delete-property/ assigned-clock-parents;
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clock-names = "clk_xin";
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clocks = <&clk_200mhz>;
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ti,driver-strength-ohm = <50>;
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non-removable;
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bus-width = <8>;
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};
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&main_sdhci1 {
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/delete-property/ power-domains;
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/delete-property/ assigned-clocks;
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/delete-property/ assigned-clock-parents;
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pinctrl-names = "default";
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pinctrl-0 = <&main_mmc1_pins_default>;
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clock-names = "clk_xin";
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clocks = <&clk_200mhz>;
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ti,driver-strength-ohm = <50>;
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};
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&wkup_i2c0 {
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u-boot,dm-spl;
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tps659413a: tps659413a@48 {
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reg = <0x48>;
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compatible = "ti,tps659413";
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u-boot,dm-spl;
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pinctrl-names = "default";
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pinctrl-0 = <&wkup_i2c0_pins_default>;
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clock-frequency = <400000>;
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regulators: regulators {
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u-boot,dm-spl;
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buck12_reg: buck12 {
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/*VDD_CPU*/
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regulator-name = "buck12";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <900000>;
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regulator-always-on;
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regulator-boot-on;
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u-boot,dm-spl;
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};
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};
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};
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};
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&wkup_vtm0 {
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vdd-supply-2 = <&buck12_reg>;
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u-boot,dm-spl;
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};
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&usbss0 {
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/delete-property/ power-domains;
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/delete-property/ assigned-clocks;
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/delete-property/ assigned-clock-parents;
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clocks = <&clk_19_2mhz>;
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clock-names = "ref";
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pinctrl-names = "default";
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pinctrl-0 = <&main_usbss0_pins_default>;
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ti,vbus-divider;
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};
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&main_i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_i2c0_pins_default>;
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clock-frequency = <400000>;
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exp1: gpio@20 {
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compatible = "ti,tca6416";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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exp2: gpio@22 {
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compatible = "ti,tca6424";
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reg = <0x22>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&hbmc {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
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reg = <0x0 0x47040000 0x0 0x100>,
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<0x0 0x50000000 0x0 0x8000000>;
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ranges = <0x0 0x0 0x0 0x50000000 0x4000000>, /* 64MB Flash on CS0 */
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<0x1 0x0 0x0 0x54000000 0x800000>; /* 8MB flash on CS1 */
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flash@0,0 {
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compatible = "cypress,hyperflash", "cfi-flash";
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reg = <0x0 0x0 0x4000000>;
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};
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};
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&ospi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
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reg = <0x0 0x47040000 0x0 0x100>,
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<0x0 0x50000000 0x0 0x8000000>;
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flash@0{
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compatible = "jedec,spi-nor";
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reg = <0x0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <8>;
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spi-max-frequency = <50000000>;
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cdns,tshsl-ns = <60>;
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cdns,tsd2d-ns = <60>;
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cdns,tchsh-ns = <60>;
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cdns,tslch-ns = <60>;
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cdns,read-delay = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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&ospi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
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u-boot,dm-spl;
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reg = <0x0 0x47050000 0x0 0x100>,
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<0x0 0x58000000 0x0 0x8000000>;
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flash@0{
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compatible = "jedec,spi-nor";
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reg = <0x0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <40000000>;
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cdns,tshsl-ns = <60>;
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cdns,tsd2d-ns = <60>;
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cdns,tchsh-ns = <60>;
|
|
cdns,tslch-ns = <60>;
|
|
cdns,read-delay = <2>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
|
|
&mcu_ringacc {
|
|
ti,sci = <&dm_tifs>;
|
|
};
|
|
|
|
&mcu_udmap {
|
|
ti,sci = <&dm_tifs>;
|
|
};
|
|
|
|
&wiz0_pll1_refclk {
|
|
assigned-clocks = <&wiz0_pll1_refclk>;
|
|
assigned-clock-parents = <&cmn_refclk1>;
|
|
};
|
|
|
|
&wiz0_refclk_dig {
|
|
assigned-clocks = <&wiz0_refclk_dig>;
|
|
assigned-clock-parents = <&cmn_refclk1>;
|
|
};
|
|
|
|
&serdes0 {
|
|
assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
|
|
assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
|
|
|
|
serdes0_pcie_link: link@0 {
|
|
reg = <0>;
|
|
cdns,num-lanes = <1>;
|
|
#phy-cells = <0>;
|
|
cdns,phy-type = <PHY_TYPE_PCIE>;
|
|
resets = <&serdes_wiz0 1>;
|
|
};
|
|
|
|
serdes0_qsgmii_link: phy@1 {
|
|
reg = <1>;
|
|
cdns,num-lanes = <1>;
|
|
#phy-cells = <0>;
|
|
cdns,phy-type = <PHY_TYPE_QSGMII>;
|
|
resets = <&serdes_wiz0 2>;
|
|
};
|
|
};
|
|
|
|
/* EEPROM might be read before SYSFW is available */
|
|
&wkup_i2c0 {
|
|
/delete-property/ power-domains;
|
|
};
|