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https://github.com/AsahiLinux/u-boot
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61693acbce
Perform a simple rename of CONFIG_USART_ID to CFG_USART_ID Signed-off-by: Tom Rini <trini@konsulko.com>
108 lines
2.8 KiB
C
108 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* (C) Copyright 2010
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* Achim Ehrlich <aehrlich@taskit.de>
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* taskit GmbH <www.taskit.de>
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*
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* (C) Copyright 2012
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* Markus Hubig <mhubig@imko.de>
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* IMKO GmbH <www.imko.de>
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*
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* (C) Copyright 2014
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* Heiko Schocher <hs@denx.de>
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* DENX Software Engineering GmbH
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*
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* Configuation settings for the smartweb.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* SoC must be defined first, before hardware.h is included.
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* In this case SoC is defined in boards.cfg.
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*/
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#include <asm/hardware.h>
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#include <linux/sizes.h>
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/*
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* Warning: changing CONFIG_TEXT_BASE requires adapting the initial boot
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* program. Since the linker has to swallow that define, we must use a pure
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* hex number here!
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*/
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/* ARM asynchronous clock */
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#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
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#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */
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/* misc settings */
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/*
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* SDRAM: 1 bank, 64 MB, base address 0x20000000
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* Already initialized before u-boot gets started.
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*/
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#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
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#define CFG_SYS_SDRAM_SIZE (64 * SZ_1M)
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/*
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* Perform a SDRAM Memtest from the start of SDRAM
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* till the beginning of the U-Boot position in RAM.
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*/
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/* NAND flash settings */
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#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
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#define CFG_SYS_NAND_MASK_ALE (1 << 21)
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#define CFG_SYS_NAND_MASK_CLE (1 << 22)
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#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
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#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC13
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/* serial console */
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#define CFG_USART_BASE ATMEL_BASE_DBGU
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#define CFG_USART_ID ATMEL_ID_SYS
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/* DFU class support */
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#define DFU_MANIFEST_POLL_TIMEOUT 25000
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/* General Boot Parameter */
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/*
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* Predefined environment variables.
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* Usefull to define some easy to use boot commands.
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*/
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#define CFG_EXTRA_ENV_SETTINGS \
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\
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"basicargs=console=ttyS0,115200\0" \
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\
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/*
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* Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
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* leaving the correct space for initial global data structure above that
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* address while providing maximum stack area below.
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*/
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#define CFG_SYS_INIT_RAM_SIZE 0x1000
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#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
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/* Defines for SPL */
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#define CFG_SYS_NAND_U_BOOT_SIZE SZ_512K
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#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
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#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
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#define CFG_SYS_NAND_ECCSIZE 256
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#define CFG_SYS_NAND_ECCBYTES 3
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#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
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48, 49, 50, 51, 52, 53, 54, 55, \
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56, 57, 58, 59, 60, 61, 62, 63, }
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#define CFG_SYS_MASTER_CLOCK (198656000/2)
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#define AT91_PLL_LOCK_TIMEOUT 1000000
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#define CFG_SYS_AT91_PLLA 0x2060bf09
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#define CFG_SYS_MCKR 0x100
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#define CFG_SYS_MCKR_CSS (0x02 | CFG_SYS_MCKR)
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#define CFG_SYS_AT91_PLLB 0x10483f0e
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#endif /* __CONFIG_H */
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