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https://github.com/AsahiLinux/u-boot
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e8f65763ef
If the OOB size is not multiple of the cache line size, the ARMv7 cache operation still prints "Misaligned operation at range". => nand info Device 0: nand0, sector size 256 KiB Page size 4096 b OOB size 224 b Erase size 262144 b subpagesize 4096 b options 0x00104200 bbt options 0x00060000 => nand dump 0 CACHE: Misaligned operation at range [9fb15280, 9fb16360] CACHE: Misaligned operation at range [9fb15280, 9fb16360] CACHE: Misaligned operation at range [9fb15280, 9fb16360] CACHE: Misaligned operation at range [9fb15280, 9fb16360] ... The cache flushing operations won't happen in this case to cover all of the range to fix this by making sure we have things aligned. Reported-by: Marek Vasut <marex@denx.de> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Reword the commit message to be clear this is a direct problem rather than just a warning] |
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| .. | ||
| nand | ||
| onenand | ||
| spi | ||
| ubi | ||
| ubispl | ||
| altera_qspi.c | ||
| cfi_flash.c | ||
| cfi_mtd.c | ||
| jedec_flash.c | ||
| Kconfig | ||
| Makefile | ||
| mtd-uclass.c | ||
| mtd_uboot.c | ||
| mtdconcat.c | ||
| mtdcore.c | ||
| mtdcore.h | ||
| mtdpart.c | ||
| mw_eeprom.c | ||
| pic32_flash.c | ||
| renesas_rpc_hf.c | ||
| st_smi.c | ||
| stm32_flash.c | ||
| stm32_flash.h | ||