mirror of
https://github.com/AsahiLinux/u-boot
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5bf0f7f65d
Now we have enabled PCIe root port on Quark SoC, add its PIRQ routing information in the device tree as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
138 lines
3.1 KiB
Text
138 lines
3.1 KiB
Text
/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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#include <dt-bindings/mrc/quark.h>
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#include <dt-bindings/interrupt-router/intel-irq.h>
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/include/ "skeleton.dtsi"
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/include/ "rtc.dtsi"
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/ {
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model = "Intel Galileo";
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compatible = "intel,galileo", "intel,quark";
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aliases {
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spi0 = "/spi";
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};
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config {
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silent_console = <0>;
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};
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chosen {
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stdout-path = &pciuart0;
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};
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mrc {
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compatible = "intel,quark-mrc";
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flags = <MRC_FLAG_SCRAMBLE_EN>;
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dram-width = <DRAM_WIDTH_X8>;
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dram-speed = <DRAM_FREQ_800>;
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dram-type = <DRAM_TYPE_DDR3>;
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rank-mask = <DRAM_RANK(0)>;
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chan-mask = <DRAM_CHANNEL(0)>;
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chan-width = <DRAM_CHANNEL_WIDTH_X16>;
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addr-mode = <DRAM_ADDR_MODE0>;
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refresh-rate = <DRAM_REFRESH_RATE_785US>;
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sr-temp-range = <DRAM_SRT_RANGE_NORMAL>;
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ron-value = <DRAM_RON_34OHM>;
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rtt-nom-value = <DRAM_RTT_NOM_120OHM>;
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rd-odt-value = <DRAM_RD_ODT_OFF>;
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dram-density = <DRAM_DENSITY_1G>;
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dram-cl = <6>;
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dram-ras = <0x0000927c>;
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dram-wtr = <0x00002710>;
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dram-rrd = <0x00002710>;
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dram-faw = <0x00009c40>;
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};
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pci {
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#address-cells = <3>;
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#size-cells = <2>;
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compatible = "pci-x86";
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u-boot,dm-pre-reloc;
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ranges = <0x02000000 0x0 0x90000000 0x90000000 0 0x20000000
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0x42000000 0x0 0xb0000000 0xb0000000 0 0x20000000
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0x01000000 0x0 0x2000 0x2000 0 0xe000>;
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pciuart0: uart@14,5 {
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compatible = "pci8086,0936.00",
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"pci8086,0936",
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"pciclass,070002",
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"pciclass,0700",
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"x86-uart";
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u-boot,dm-pre-reloc;
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reg = <0x0000a500 0x0 0x0 0x0 0x0
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0x0200a510 0x0 0x0 0x0 0x0>;
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reg-shift = <2>;
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clock-frequency = <44236800>;
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current-speed = <115200>;
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};
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irq-router@1f,0 {
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reg = <0x0000f800 0 0 0 0>;
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compatible = "intel,irq-router";
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intel,pirq-config = "pci";
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intel,pirq-link = <0x60 8>;
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intel,pirq-mask = <0xdef8>;
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intel,pirq-routing = <
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PCI_BDF(0, 20, 0) INTA PIRQE
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PCI_BDF(0, 20, 1) INTB PIRQF
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PCI_BDF(0, 20, 2) INTC PIRQG
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PCI_BDF(0, 20, 3) INTD PIRQH
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PCI_BDF(0, 20, 4) INTA PIRQE
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PCI_BDF(0, 20, 5) INTB PIRQF
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PCI_BDF(0, 20, 6) INTC PIRQG
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PCI_BDF(0, 20, 7) INTD PIRQH
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PCI_BDF(0, 21, 0) INTA PIRQE
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PCI_BDF(0, 21, 1) INTB PIRQF
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PCI_BDF(0, 21, 2) INTC PIRQG
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PCI_BDF(0, 23, 0) INTA PIRQA
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PCI_BDF(0, 23, 1) INTB PIRQB
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/* PCIe root ports downstream interrupts */
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PCI_BDF(1, 0, 0) INTA PIRQA
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PCI_BDF(1, 0, 0) INTB PIRQB
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PCI_BDF(1, 0, 0) INTC PIRQC
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PCI_BDF(1, 0, 0) INTD PIRQD
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PCI_BDF(2, 0, 0) INTA PIRQB
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PCI_BDF(2, 0, 0) INTB PIRQC
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PCI_BDF(2, 0, 0) INTC PIRQD
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PCI_BDF(2, 0, 0) INTD PIRQA
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>;
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};
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};
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gpioa {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0 0x20>;
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bank-name = "A";
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};
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gpiob {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0x20 0x20>;
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bank-name = "B";
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};
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "intel,ich-spi";
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spi-flash@0 {
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#size-cells = <1>;
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#address-cells = <1>;
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reg = <0>;
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compatible = "winbond,w25q64", "spi-flash";
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memory-map = <0xff800000 0x00800000>;
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};
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};
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};
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