mirror of
https://github.com/AsahiLinux/u-boot
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345 lines
11 KiB
C
345 lines
11 KiB
C
/*
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* (C) Copyright 2007
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC8247 1
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#define CONFIG_MPC8272_FAMILY 1
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#define CONFIG_MGCOGE 1
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#define CONFIG_CPM2 1 /* Has a CPM2 */
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/* Do boardspecific init */
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#define CONFIG_BOARD_EARLY_INIT_R 1
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/*
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* Select serial console configuration
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*
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* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
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* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
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* for SCC).
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*/
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#define CONFIG_CONS_ON_SMC /* Console is on SMC */
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#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
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#undef CONFIG_CONS_NONE /* It's not on external UART */
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#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
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/*
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* Select ethernet configuration
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*
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* If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
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* then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
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* SCC, 1-3 for FCC)
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*
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* If CONFIG_ETHER_NONE is defined, then either the ethernet routines
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* must be defined elsewhere (as for the console), or CONFIG_CMD_NET
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* must be unset.
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*/
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#define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */
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#undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */
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#undef CONFIG_ETHER_NONE /* No external Ethernet */
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#define CONFIG_ETHER_INDEX 4
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#define CFG_SCC_TOUT_LOOP 10000000
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# define CFG_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
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#ifndef CONFIG_8260_CLKIN
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#define CONFIG_8260_CLKIN 66000000 /* in Hz */
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#endif
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#define CONFIG_BAUDRATE 115200
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ECHO
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#define CONFIG_CMD_IMMAP
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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/*
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* Default environment settings
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"u-boot_addr=100000\0" \
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"kernel_addr=200000\0" \
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"fdt_addr=400000\0" \
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"rootpath=/opt/eldk-4.2/ppc_82xx\0" \
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"u-boot=/tftpboot/mgcoge/u-boot.bin\0" \
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"bootfile=/tftpboot/mgcoge/uImage\0" \
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"fdt_file=/tftpboot/mgcoge/mgcoge.dtb\0" \
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"load=tftp ${u-boot_addr} ${u-boot}\0" \
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"update=prot off fe000000 fe03ffff; era fe000000 fe03ffff; " \
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"cp.b ${u-boot_addr} fe000000 ${filesize};" \
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"prot on fe000000 fe03ffff\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \
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"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:" \
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"${netmask}:${hostname}:${netdev}:off panic=1\0" \
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"net_nfs=tftp ${kernel_addr} ${bootfile}; " \
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"tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcons;" \
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"bootm ${kernel_addr} - ${fdt_addr}\0" \
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"net_self=tftp ${kernel_addr} ${bootfile}; " \
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"tftp ${fdt_addr} ${fdt_file}; " \
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"tftp ${ramdisk_addr} ${ramdisk_file}; " \
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"run ramargs addip; " \
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"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
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""
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#define CONFIG_BOOTCOMMAND "run net_nfs"
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
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#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0xFE000000
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#define CFG_FLASH_SIZE 32
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#define CFG_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */
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#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
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#define CFG_FLASH_BASE_1 0x50000000
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#define CFG_FLASH_SIZE_1 64
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#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE_1 }
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#define CFG_MONITOR_BASE TEXT_BASE
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#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
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#define CFG_RAMBOOT
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#endif
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
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#define CONFIG_ENV_IS_IN_FLASH
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#ifdef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
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#endif /* CONFIG_ENV_IS_IN_FLASH */
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#define CFG_IMMR 0xF0000000
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/* Hard reset configuration word */
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#define CFG_HRCW_MASTER 0x0604b211
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/* No slaves */
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#define CFG_HRCW_SLAVE1 0
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#define CFG_HRCW_SLAVE2 0
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#define CFG_HRCW_SLAVE3 0
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#define CFG_HRCW_SLAVE4 0
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#define CFG_HRCW_SLAVE5 0
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#define CFG_HRCW_SLAVE6 0
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#define CFG_HRCW_SLAVE7 0
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
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#if defined(CONFIG_CMD_KGDB)
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# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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#define CFG_HID0_INIT 0
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#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
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#define CFG_HID2 0
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#define CFG_SIUMCR 0x4020c200
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#define CFG_SYPCR 0xFFFFFFC3
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#define CFG_BCR 0x10000000
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#define CFG_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK)
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/*-----------------------------------------------------------------------
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* RMR - Reset Mode Register 5-5
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*-----------------------------------------------------------------------
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* turn on Checkstop Reset Enable
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*/
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#define CFG_RMR 0
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/*-----------------------------------------------------------------------
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* TMCNTSC - Time Counter Status and Control 4-40
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*-----------------------------------------------------------------------
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* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
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* and enable Time Counter
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*/
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#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 4-42
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
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* Periodic timer
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*/
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#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
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/*-----------------------------------------------------------------------
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* RCCR - RISC Controller Configuration 13-7
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*-----------------------------------------------------------------------
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*/
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#define CFG_RCCR 0
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/*
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* Init Memory Controller:
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*
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* Bank Bus Machine PortSz Device
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* ---- --- ------- ------ ------
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* 0 60x GPCM 8 bit FLASH
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* 1 60x SDRAM 32 bit SDRAM
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* 3 60x GPCM 8 bit GPIO/PIGGY
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* 5 60x GPCM 16 bit CFG-Flash
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*
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*/
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/* Bank 0 - FLASH
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*/
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#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
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BRx_PS_8 |\
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BRx_MS_GPCM_P |\
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BRx_V)
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#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\
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ORxG_CSNT |\
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ORxG_ACS_DIV2 |\
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ORxG_SCY_5_CLK |\
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ORxG_TRLX )
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/* Bank 1 - 60x bus SDRAM
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*/
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#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
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#define CFG_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */
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#define CFG_MPTPR 0x1800
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/*-----------------------------------------------------------------------------
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* Address for Mode Register Set (MRS) command
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*-----------------------------------------------------------------------------
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*/
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#define CFG_MRS_OFFS 0x00000110
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#define CFG_PSRT 0x0e
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#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
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BRx_PS_64 |\
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BRx_MS_SDRAM_P |\
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BRx_V)
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#define CFG_OR1_PRELIM CFG_OR1
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/* SDRAM initialization values
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*/
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#define CFG_OR1 ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
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ORxS_BPD_8 |\
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ORxS_ROWST_PBI0_A7 |\
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ORxS_NUMR_13)
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#define CFG_PSDMR (PSDMR_SDAM_A14_IS_A5 |\
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PSDMR_BSMA_A14_A16 |\
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PSDMR_SDA10_PBI0_A9 |\
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PSDMR_RFRC_5_CLK |\
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PSDMR_PRETOACT_2W |\
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PSDMR_ACTTORW_2W |\
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PSDMR_LDOTOPRE_1C |\
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PSDMR_WRC_1C |\
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PSDMR_CL_2)
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/* GPIO/PIGGY on CS3 initialization values
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*/
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#define CFG_PIGGY_BASE 0x30000000
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#define CFG_PIGGY_SIZE 128
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#define CFG_BR3_PRELIM ((CFG_PIGGY_BASE & BRx_BA_MSK) |\
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BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
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#define CFG_OR3_PRELIM (MEG_TO_AM(CFG_PIGGY_SIZE) |\
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ORxG_CSNT | ORxG_ACS_DIV2 |\
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ORxG_SCY_3_CLK | ORxG_TRLX )
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/* CFG-Flash on CS5 initialization values
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*/
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#define CFG_BR5_PRELIM ((CFG_FLASH_BASE_1 & BRx_BA_MSK) |\
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BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
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#define CFG_OR5_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE_1) |\
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ORxG_CSNT | ORxG_ACS_DIV2 |\
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ORxG_SCY_5_CLK | ORxG_TRLX )
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#define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#define OF_CPU "PowerPC,8247@0"
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#define OF_SOC "soc@f0000000"
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#define OF_TBCLK (bd->bi_busfreq / 4)
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#define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
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#endif /* __CONFIG_H */
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