mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-15 07:43:07 +00:00
9bd954ab8a
The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with the on-board NIC chip changed from rtl8211e to yt8531c, and RAM type changed from DDR4 to LPDDR3. The device tree is taken from kernel v6.4-rc1. Signed-off-by: Tianling Shen <cnsztl@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
46 lines
716 B
Text
46 lines
716 B
Text
// SPDX-License-Identifier: GPL-2.0-or-later
|
|
/*
|
|
* (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
|
|
* (C) Copyright 2020 David Bauer
|
|
*/
|
|
|
|
#include "rk3328-u-boot.dtsi"
|
|
#include "rk3328-sdram-lpddr3-666.dtsi"
|
|
/ {
|
|
chosen {
|
|
u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
|
|
};
|
|
};
|
|
|
|
&gpio0 {
|
|
bootph-pre-ram;
|
|
};
|
|
|
|
&pinctrl {
|
|
bootph-pre-ram;
|
|
};
|
|
|
|
&sdmmc0m1_pin {
|
|
bootph-pre-ram;
|
|
};
|
|
|
|
&pcfg_pull_up_4ma {
|
|
bootph-pre-ram;
|
|
};
|
|
|
|
/* Need this and all the pinctrl/gpio stuff above to set pinmux */
|
|
&vcc_sd {
|
|
bootph-pre-ram;
|
|
};
|
|
|
|
&gmac2io {
|
|
snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
|
|
snps,reset-active-low;
|
|
snps,reset-delays-us = <0 10000 50000>;
|
|
};
|
|
|
|
&spi0 {
|
|
spi_flash: spiflash@0 {
|
|
bootph-all;
|
|
};
|
|
};
|