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https://github.com/AsahiLinux/u-boot
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250f745ae8
Pick up the serial node descriptions from Linux v6.3 for the ls1046ardb and ls1046afrwy boards and their dependencies. Including the fsl,qoriq-clockgen.h and arm-gic.h headers forces us to change the include directives to explicitly go through the C preprocessor for all boards in the ls1046a SoC family. Signed-off-by: Camelia Groza <camelia.groza@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
102 lines
1.4 KiB
Text
102 lines
1.4 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* Device Tree Include file for NXP Layerscape-1046A family SoC.
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*
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* Copyright 2019-2023 NXP
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*
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*/
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/dts-v1/;
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#include "fsl-ls1046a.dtsi"
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/ {
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model = "LS1046A FRWY Board";
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aliases {
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spi0 = &qspi;
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serial0 = &duart0;
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serial1 = &duart1;
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serial2 = &duart2;
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serial3 = &duart3;
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};
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};
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&duart0 {
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status = "okay";
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};
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&duart1 {
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status = "okay";
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};
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&duart2 {
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status = "okay";
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};
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&duart3 {
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status = "okay";
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};
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&qspi {
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status = "okay";
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mt25qu512a0: flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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reg = <0>;
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};
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};
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&i2c0 {
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status = "okay";
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};
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#include "fsl-ls1046-post.dtsi"
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&fman0 {
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ethernet@e0000 {
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phy-handle = <&qsgmii_phy4>;
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phy-connection-type = "qsgmii";
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status = "okay";
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};
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ethernet@e8000 {
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phy-handle = <&qsgmii_phy2>;
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phy-connection-type = "qsgmii";
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status = "okay";
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};
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ethernet@ea000 {
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phy-handle = <&qsgmii_phy1>;
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phy-connection-type = "qsgmii";
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status = "okay";
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};
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ethernet@f2000 {
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phy-handle = <&qsgmii_phy3>;
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phy-connection-type = "qsgmii";
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status = "okay";
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};
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mdio@fd000 {
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qsgmii_phy1: ethernet-phy@1c {
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reg = <0x1c>;
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};
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qsgmii_phy2: ethernet-phy@1d {
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reg = <0x1d>;
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};
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qsgmii_phy3: ethernet-phy@1e {
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reg = <0x1e>;
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};
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qsgmii_phy4: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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};
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