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23780398b5
Update the Kconfig entry to have the correct defaults for i.MX6 platforms, and move the existing large comment from imx6_spl.h to doc/imx/common/imx6.txt so that it's not lost. Signed-off-by: Tom Rini <trini@konsulko.com>
195 lines
6.2 KiB
Text
195 lines
6.2 KiB
Text
U-Boot for Freescale i.MX6
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This file contains information for the port of U-Boot to the Freescale i.MX6
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SoC.
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1. CONVENTIONS FOR FUSE ASSIGNMENTS
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-----------------------------------
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1.1 MAC Address: It is stored in fuse bank 4, with the 32 lsbs in word 2 and the
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16 msbs in word 3[15:0].
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For i.MX6SX and i.MX6UL, they have two MAC addresses. The second MAC address
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is stored in fuse bank 4, with the 16 lsb in word 3[31:16] and the 32 msbs in
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word 4.
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Example:
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For reading the MAC address fuses on a MX6Q:
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- The MAC address is stored in two fuse addresses (the fuse addresses are
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described in the Fusemap Descriptions table from the mx6q Reference Manual):
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0x620[31:0] - MAC_ADDR[31:0]
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0x630[15:0] - MAC_ADDR[47:32]
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In order to use the fuse API, we need to pass the bank and word values, which
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are calculated as below:
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Fuse address for the lower MAC address: 0x620
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Base address for the fuses: 0x400
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(0x620 - 0x400)/0x10 = 0x22 = 34 decimal
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As the fuses are arranged in banks of 8 words:
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34 / 8 = 4 and the remainder is 2, so in this case:
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bank = 4
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word = 2
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And the U-Boot command would be:
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=> fuse read 4 2
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Reading bank 4:
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Word 0x00000002: 9f027772
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Doing the same for the upper MAC address:
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Fuse address for the upper MAC address: 0x630
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Base address for the fuses: 0x400
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(0x630 - 0x400)/0x10 = 0x23 = 35 decimal
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As the fuses are arranged in banks of 8 words:
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35 / 8 = 4 and the remainder is 3, so in this case:
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bank = 4
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word = 3
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And the U-Boot command would be:
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=> fuse read 4 3
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Reading bank 4:
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Word 0x00000003: 00000004
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,which matches the ethaddr value:
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=> echo ${ethaddr}
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00:04:9f:02:77:72
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Some other useful hints:
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- The 'bank' and 'word' numbers can be easily obtained from the mx6 Reference
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Manual. For the mx6quad case, please check the "46.5 OCOTP Memory Map/Register
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Definition" from the "i.MX 6Dual/6Quad Applications Processor Reference Manual,
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Rev. 1, 04/2013" document. For example, for the MAC fuses we have:
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Address:
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21B_C620 Value of OTP Bank4 Word2 (MAC Address)(OCOTP_MAC0)
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21B_C630 Value of OTP Bank4 Word3 (MAC Address)(OCOTP_MAC1)
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- The command '=> fuse read 4 2 2' reads the whole MAC addresses at once:
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=> fuse read 4 2 2
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Reading bank 4:
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Word 0x00000002: 9f027772 00000004
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NAND Boot on i.MX6 with SPL support
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--------------------------------------
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Writing/updating boot image in nand device is not straight forward in
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i.MX6 platform and it requires boot control block(BCB) to be configured.
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BCB contains two data structures, Firmware Configuration Block(FCB) and
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Discovered Bad Block Table(DBBT). FCB has nand timings, DBBT search area,
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and firmware. See IMX6DQRM Section 8.5.2.2
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for more information.
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We can't use 'nand write' command to write SPL/firmware image directly
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like other platforms does. So we need special setup to write BCB block
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as per IMX6QDL reference manual 'nandbcb update' command do that job.
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for nand boot, up on reset bootrom look for FCB structure in
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first block's if FCB found the nand timings are loaded for
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further reads. once FCB read done, DTTB will be loaded and
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finally firmware will be loaded which is boot image.
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cmd_nandbcb will create FCB these structures
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by taking mtd partition as an example.
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- initial code will erase entire partition
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- followed by FCB setup, like first 2 blocks for FCB/DBBT write,
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and next block for FW1/SPL
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- write firmware at FW1 block and
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- finally write fcb/dttb in first 2 block.
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Typical NAND BCB layout:
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=======================
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no.of blocks = partition size / erasesize
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no.of fcb/dbbt blocks = 2
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FW1 offset = no.of fcb/dbbt
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block 0 1 2
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-------------------------------
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|FCB/DBBT 0|FCB/DBBT 1| FW 1 |
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--------------------------------
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On summary, nandbcb update will
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- erase the entire partition
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- create BCB by creating 2 FCB/BDDT block followed by
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1 FW blocks based on partition size and erasesize.
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- fill FCB/DBBT structures
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- write FW/SPL in FW1
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- write FCB/DBBT in first 2 blocks
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step-1: write SPL
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icorem6qdl> ext4load mmc 0:1 $loadaddr SPL
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39936 bytes read in 10 ms (3.8 MiB/s)
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icorem6qdl> nandbcb update $loadaddr spl $filesize
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device 0 offset 0x0, size 0x9c00
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Erasing at 0x1c0000 -- 100% complete.
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NAND fw write: 0x80000 offset, 0xb000 bytes written: OK
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step-2: write u-boot-dtb.img
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icorem6qdl> nand erase.part uboot
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NAND erase.part: device 0 offset 0x200000, size 0x200000
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Erasing at 0x3c0000 -- 100% complete.
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OK
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icorem6qdl> ext4load mmc 0:1 $loadaddr u-boot-dtb.img
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589094 bytes read in 37 ms (15.2 MiB/s)
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icorem6qdl> nand write ${loadaddr} uboot ${filesize}
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NAND write: device 0 offset 0x200000, size 0x8fd26
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589094 bytes written: OK
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icorem6qdl>
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SPL Stack size and location notes
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---------------------------------
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If we have CONFIG_MX6_OCRAM_256KB then see Figure 8.4.1 in IMX6DQ Reference
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manuals:
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- IMX6DQ OCRAM (IRAM) is from 0x00907000 to 0x0093FFFF
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- BOOT ROM stack is at 0x0093FFB8
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- if icache/dcache is enabled (eFuse/strapping controlled) then the
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IMX BOOT ROM will setup MMU table at 0x00938000, therefore we need to
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fit between 0x00907000 and 0x00938000.
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- Additionally the BOOT ROM loads what they consider the firmware image
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which consists of a 4K header in front of us that contains the IVT, DCD
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and some padding thus 'our' max size is really 0x00908000 - 0x00938000
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or 192KB
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- Pad SPL to 196KB (4KB header + 192KB max size). This allows to write the
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SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a
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boot media (given that boot media specific offset is configured properly).
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and if we don't, see Figure 8-3 in IMX6SDL Reference manuals:
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- IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF
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- BOOT ROM stack is at 0x0091FFB8
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- if icache/dcache is enabled (eFuse/strapping controlled) then the
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IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to
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fit between 0x00907000 and 0x00918000.
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- Additionally the BOOT ROM loads what they consider the firmware image
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which consists of a 4K header in front of us that contains the IVT, DCD
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and some padding thus 'our' max size is really 0x00908000 - 0x00918000
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or 64KB
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- Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the
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SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a
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boot media (given that boot media specific offset is configured properly).
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