mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-02 01:19:49 +00:00
d1c1ba85c7
This patch adds fdt (flattened device tree) support to the AMCC Acadia eval board. This increases the image size and it doesn't fit anymore into 256kByte. Since we didn't want to remove features from the configuration, we decided to increase the U-Boot image size (add one flash sector). Also changed the default environment definition to make it independent of such changes. Signed-off-by: Stefan Roese <sr@denx.de>
513 lines
19 KiB
C
513 lines
19 KiB
C
/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/************************************************************************
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* acadia.h - configuration for AMCC Acadia (405EZ)
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***********************************************************************/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*-----------------------------------------------------------------------
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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#define CONFIG_ACADIA 1 /* Board is Acadia */
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_405EZ 1 /* Specifc 405EZ support*/
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/* Detect Acadia PLL input clock automatically via CPLD bit */
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#define CONFIG_SYS_CLK_FREQ ((in8(CFG_CPLD_BASE + 0) == 0x0c) ? \
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66666666 : 33333000)
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_MISC_INIT_F 1 /* Call misc_init_f */
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#define CONFIG_NO_SERIAL_EEPROM
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/*#undef CONFIG_NO_SERIAL_EEPROM*/
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#ifdef CONFIG_NO_SERIAL_EEPROM
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/*----------------------------------------------------------------------------
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* PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
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* assuming a 66MHz input clock to the 405EZ.
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*---------------------------------------------------------------------------*/
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/* #define PLLMR0_100_100_12 */
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#define PLLMR0_200_133_66
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/* #define PLLMR0_266_160_80 */
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/* #define PLLMR0_333_166_83 */
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#endif
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0xfe000000
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#define CFG_CPLD_BASE 0x80000000
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#define CFG_NAND_ADDR 0xd0000000
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#define CFG_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MONITOR_LEN (0xFFFFFFFF - CFG_MONITOR_BASE + 1)
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#define CFG_MALLOC_LEN (512 * 1024)/* Reserve 512 kB for malloc() */
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/*-----------------------------------------------------------------------
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* Initial RAM & stack pointer
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*----------------------------------------------------------------------*/
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#define CFG_TEMP_STACK_OCM 1 /* OCM as init ram */
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/* On Chip Memory location */
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#define CFG_OCM_DATA_ADDR 0xf8000000
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#define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */
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#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */
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#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
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#define CFG_GBL_DATA_SIZE 128 /* size for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Serial Port
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*----------------------------------------------------------------------*/
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#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
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#define CFG_BASE_BAUD 691200
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SERIAL_MULTI 1
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/* The following table includes the supported baudrates */
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
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/*-----------------------------------------------------------------------
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* Environment
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*----------------------------------------------------------------------*/
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#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
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#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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#else
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#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
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#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
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#endif
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/*-----------------------------------------------------------------------
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* FLASH related
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*----------------------------------------------------------------------*/
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#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
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#define CFG_FLASH_CFI /* The flash is CFI compatible */
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#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#else
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#define CFG_NO_FLASH 1 /* No NOR on Acadia when NAND-booting */
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#endif
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#ifdef CFG_ENV_IS_IN_FLASH
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#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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#endif
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/*
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* IPL (Initial Program Loader, integrated inside CPU)
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* Will load first 4k from NAND (SPL) into cache and execute it from there.
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*
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* SPL (Secondary Program Loader)
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* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
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* has to fit into 4kByte. It sets up the CPU and configures the SDRAM
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* controller and the NAND controller so that the special U-Boot image can be
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* loaded from NAND to SDRAM.
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*
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* NUB (NAND U-Boot)
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* This NAND U-Boot (NUB) is a special U-Boot version which can be started
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* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
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*
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* On 440EPx the SPL is copied to SDRAM before the NAND controller is
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* set up. While still running from cache, I experienced problems accessing
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* the NAND controller. sr - 2006-08-25
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*/
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#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
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#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
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#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/
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#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
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#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
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#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
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/*
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* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
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*/
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#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
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#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
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/*
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* Now the NAND chip has to be defined (no autodetection used!)
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*/
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#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
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#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
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#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
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#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
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#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
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#define CFG_NAND_ECCSIZE 256
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#define CFG_NAND_ECCBYTES 3
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#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
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#define CFG_NAND_OOBSIZE 16
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#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
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#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
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#ifdef CFG_ENV_IS_IN_NAND
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/*
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* For NAND booting the environment is embedded in the U-Boot image. Please take
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* look at the file board/amcc/sequoia/u-boot-nand.lds for details.
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*/
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#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE
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#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
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#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
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#endif
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/*-----------------------------------------------------------------------
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* RAM (CRAM)
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*----------------------------------------------------------------------*/
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#define CFG_MBYTES_RAM 64 /* 64MB */
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/*-----------------------------------------------------------------------
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* I2C
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*----------------------------------------------------------------------*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_MULTI_EEPROMS
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#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
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#define CFG_I2C_EEPROM_ADDR_LEN 1
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#define CFG_EEPROM_PAGE_WRITE_ENABLE
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#define CFG_EEPROM_PAGE_WRITE_BITS 3
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
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/* I2C SYSMON (LM75, AD7414 is almost compatible) */
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#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
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#define CONFIG_DTT_AD7414 1 /* use AD7414 */
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#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
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#define CFG_DTT_MAX_TEMP 70
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#define CFG_DTT_LOW_TEMP -30
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#define CFG_DTT_HYSTERESIS 3
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#if 0 /* test-only... */
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/*-----------------------------------------------------------------------
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* SPI stuff - Define to include SPI control
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SPI
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#endif
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/*-----------------------------------------------------------------------
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* Ethernet
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*----------------------------------------------------------------------*/
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0 /* PHY address */
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#define CONFIG_NET_MULTI 1
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#define CFG_RX_ETH_BUFFER 16 /* # of rx buffers & descriptors*/
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#define CONFIG_HAS_ETH0 1
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#define CONFIG_NETCONSOLE /* include NetConsole support */
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#define xstr(s) str(s)
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#define str(s) #s
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"hostname=acadia\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
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"flash_nfs=run nfsargs addip addtty;" \
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"bootm ${kernel_addr}\0" \
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"flash_self=run ramargs addip addtty;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
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"bootm\0" \
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"rootpath=/opt/eldk/ppc_4xx\0" \
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"bootfile=acadia/uImage\0" \
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"kernel_addr=fff10000\0" \
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"ramdisk_addr=fff20000\0" \
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"initrd_high=30000000\0" \
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"load=tftp 200000 acadia/u-boot.bin\0" \
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"update=protect off " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \
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"era " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \
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"cp.b ${fileaddr} " xstr(CFG_MONITOR_BASE) " ${filesize};" \
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"setenv filesize;saveenv\0" \
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"upd=run load update\0" \
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"nload=tftp 200000 acadia/u-boot-nand.bin\0" \
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"nupdate=nand erase 0 60000;nand write 200000 0 60000;" \
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"setenv filesize;saveenv\0" \
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"nupd=run nload nupdate\0" \
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"kozio=bootm ffc60000\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_self"
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_USB_OHCI
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#define CONFIG_USB_STORAGE
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/* Partitions */
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_ISO_PARTITION
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#define CONFIG_SUPPORT_VFAT
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DTT
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_USB
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/*
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* No NOR on Acadia when NAND-booting
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*/
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#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
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#undef CONFIG_CMD_FLASH
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#undef CONFIG_CMD_IMLS
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#endif
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*-----------------------------------------------------------------------
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* Miscellaneous configurable options
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*----------------------------------------------------------------------*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_LOOPW 1 /* enable loopw command */
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#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* NAND FLASH
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*----------------------------------------------------------------------*/
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#define CFG_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
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#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
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/*-----------------------------------------------------------------------
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* External Bus Controller (EBC) Setup
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*----------------------------------------------------------------------*/
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#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
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#define CFG_NAND_CS 3
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/* Memory Bank 0 (Flash) initialization */
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#define CFG_EBC_PB0AP 0x03337200
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#define CFG_EBC_PB0CR 0xfe0bc000
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/* Memory Bank 3 (NAND-FLASH) initialization */
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#define CFG_EBC_PB3AP 0x018003c0
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#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000)
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/* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/
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/* Memory Bank 1 (CRAM) initialization */
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#define CFG_EBC_PB1AP 0x030400c0
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#define CFG_EBC_PB1CR 0x000bc000
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/* Memory Bank 2 (CRAM) initialization */
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#define CFG_EBC_PB2AP 0x030400c0
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#define CFG_EBC_PB2CR 0x020bc000
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#else
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#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
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/* Memory Bank 0 (NAND-FLASH) initialization */
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#define CFG_EBC_PB0AP 0x018003c0
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#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000)
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/*
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* When NAND-booting the CRAM EBC setup must be done in sync mode, since the
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* NAND-SPL already initialized the CRAM and EBC to sync mode.
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*/
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/* Memory Bank 1 (CRAM) initialization */
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#define CFG_EBC_PB1AP 0x9C0201C0
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#define CFG_EBC_PB1CR 0x000bc000
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/* Memory Bank 2 (CRAM) initialization */
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#define CFG_EBC_PB2AP 0x9C0201C0
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#define CFG_EBC_PB2CR 0x020bc000
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#endif
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/* Memory Bank 4 (CPLD) initialization */
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#define CFG_EBC_PB4AP 0x04006000
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#define CFG_EBC_PB4CR (CFG_CPLD_BASE | 0x18000)
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#define CFG_EBC_CFG 0xf8400000
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/*-----------------------------------------------------------------------
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* GPIO Setup
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*----------------------------------------------------------------------*/
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#define CFG_GPIO_CRAM_CLK 8
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#define CFG_GPIO_CRAM_WAIT 9 /* GPIO-In */
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#define CFG_GPIO_CRAM_ADV 10
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#define CFG_GPIO_CRAM_CRE (32 + 21) /* GPIO-Out */
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/*-----------------------------------------------------------------------
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* Definitions for GPIO_0 setup (PPC405EZ specific)
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*
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* GPIO0[0-2] - External Bus Controller CS_4 - CS_6 Outputs
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* GPIO0[3] - NAND FLASH Controller CE3 (NFCE3) Output
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* GPIO0[4] - External Bus Controller Hold Input
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* GPIO0[5] - External Bus Controller Priority Input
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* GPIO0[6] - External Bus Controller HLDA Output
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* GPIO0[7] - External Bus Controller Bus Request Output
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* GPIO0[8] - CRAM Clk Output
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* GPIO0[9] - External Bus Controller Ready Input
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* GPIO0[10] - CRAM Adv Output
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* GPIO0[11-24] - NAND Flash Control Data -> Bypasses GPIO when enabled
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* GPIO0[25] - External DMA Request Input
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* GPIO0[26] - External DMA EOT I/O
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* GPIO0[25] - External DMA Ack_n Output
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* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
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* GPIO0[28-30] - Trace Outputs / PWM Inputs
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* GPIO0[31] - PWM_8 I/O
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*/
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#define CFG_GPIO0_TCR 0xC0A00000
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#define CFG_GPIO0_OSRL 0x50004400
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#define CFG_GPIO0_OSRH 0x02000055
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#define CFG_GPIO0_ISR1L 0x00001000
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#define CFG_GPIO0_ISR1H 0x00000055
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#define CFG_GPIO0_TSRL 0x02000000
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#define CFG_GPIO0_TSRH 0x00000055
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/*-----------------------------------------------------------------------
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* Definitions for GPIO_1 setup (PPC405EZ specific)
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*
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* GPIO1[0-6] - PWM_9 to PWM_15 I/O
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* GPIO1[7] - PWM_DIV_CLK (Out) / IRQ4 Input
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* GPIO1[8] - TS5 Output / DAC_IP_TRIG Input
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* GPIO1[9] - TS6 Output / ADC_IP_TRIG Input
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* GPIO1[10-12] - UART0 Control Inputs
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* GPIO1[13] - UART0_DTR_N Output/IEEE_1588_TS Output/TMRCLK Input
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* GPIO1[14] - UART0_RTS_N Output/SPI_SS_2_N Output
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* GPIO1[15] - SPI_SS_3_N Output/UART0_RI_N Input
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* GPIO1[16] - SPI_SS_1_N Output
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* GPIO1[17-20] - Trace Output/External Interrupts IRQ0 - IRQ3 inputs
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*/
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#define CFG_GPIO1_TCR 0xFFFF8414
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#define CFG_GPIO1_OSRL 0x40000110
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#define CFG_GPIO1_OSRH 0x55455555
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#define CFG_GPIO1_ISR1L 0x15555445
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#define CFG_GPIO1_ISR1H 0x00000000
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#define CFG_GPIO1_TSRL 0x00000000
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#define CFG_GPIO1_TSRH 0x00000000
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#endif /* __CONFIG_H */
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