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u-boot/arch/arm/cpu/armv8
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York Sun 2f78eae506 ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC 
Freescale LayerScape with Chassis Generation 3 is a set of SoCs with
ARMv8 cores and 3rd generation of Chassis. We use different MMU setup
to support memory map and cache attribute for these SoCs. MMU and cache
are enabled very early to bootst performance, especially for early
development on emulators. After u-boot relocates to DDR, a new MMU
table with QBMan cache access is created in DDR. SMMU pagesize is set
in SMMU_sACR register. Both DDR3 and DDR4 are supported.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-07-03 08:40:51 +02:00
..
fsl-lsch3 ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC 2014-07-03 08:40:51 +02:00
cache.S ARMv8: fix bug for flush data cache by set/way 2014-04-07 22:27:22 +02:00
cache_v8.c ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC 2014-07-03 08:40:51 +02:00
config.mk arm: Switch to -mno-unaligned-access when supported by the compiler 2014-02-26 21:19:32 +01:00
cpu.c arm64: core support 2014-01-09 16:08:44 +01:00
exceptions.S arm64: core support 2014-01-09 16:08:44 +01:00
generic_timer.c arm64: core support 2014-01-09 16:08:44 +01:00
Makefile arm64 patch: gicv3 support 2014-04-08 00:15:12 +02:00
start.S Arm64 fix a bug of vbar_el3 initialization 2014-05-25 15:26:00 +02:00
tlb.S arm64: core support 2014-01-09 16:08:44 +01:00
transition.S arm64: zero cntvoff_el2 2014-06-09 10:24:02 +02:00
u-boot.lds arm64: core support 2014-01-09 16:08:44 +01:00