mirror of
https://github.com/AsahiLinux/u-boot
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819833af39
This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
98 lines
2.6 KiB
C
98 lines
2.6 KiB
C
/*
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* UART Masks
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*/
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#ifndef __BFIN_PERIPHERAL_UART__
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#define __BFIN_PERIPHERAL_UART__
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/* UARTx_LCR Masks */
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#define WLS 0x03 /* Word Length Select */
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#define WLS_5 0x00 /* 5 bit word */
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#define WLS_6 0x01 /* 6 bit word */
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#define WLS_7 0x02 /* 7 bit word */
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#define WLS_8 0x03 /* 8 bit word */
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#define STB 0x04 /* Stop Bits */
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#define PEN 0x08 /* Parity Enable */
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#define EPS 0x10 /* Even Parity Select */
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#define STP 0x20 /* Stick Parity */
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#define SB 0x40 /* Set Break */
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#define DLAB 0x80 /* Divisor Latch Access */
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#define DLAB_P 0x07
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#define SB_P 0x06
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#define STP_P 0x05
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#define EPS_P 0x04
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#define PEN_P 0x03
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#define STB_P 0x02
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#define WLS_P1 0x01
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#define WLS_P0 0x00
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/* UARTx_MCR Mask */
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#define XOFF 0x01 /* Transmitter off */
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#define MRTS 0x02 /* Manual Request to Send */
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#define RFIT 0x04 /* Receive FIFO IRQ Threshold */
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#define RFRT 0x08 /* Receive FIFO RTS Threshold */
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#define LOOP_ENA 0x10 /* Loopback Mode Enable */
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#define FCPOL 0x20 /* Flow Control Pin Polarity */
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#define ARTS 0x40 /* Auto RTS generation for RX handshake */
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#define ACTS 0x80 /* Auto CTS operation for TX handshake */
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#define XOFF_P 0
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#define MRTS_P 1
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#define RFIT_P 2
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#define RFRT_P 3
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#define LOOP_ENA_P 4
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#define FCPOL_P 5
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#define ARTS_P 6
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#define ACTS_P 7
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/* UARTx_LSR Masks */
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#define DR 0x01 /* Data Ready */
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#define OE 0x02 /* Overrun Error */
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#define PE 0x04 /* Parity Error */
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#define FE 0x08 /* Framing Error */
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#define BI 0x10 /* Break Interrupt */
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#define THRE 0x20 /* THR Empty */
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#define TEMT 0x40 /* TSR and UART_THR Empty */
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#define DR_P 0x00
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#define OE_P 0x01
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#define PE_P 0x02
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#define FE_P 0x03
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#define BI_P 0x04
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#define THRE_P 0x05
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#define TEMT_P 0x06
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/* UARTx_IER Masks */
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#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
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#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
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#define ELSI 0x04 /* Enable RX Status Interrupt */
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#define ERBFI_P 0x00
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#define ETBEI_P 0x01
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#define ELSI_P 0x02
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/* UARTx_IIR Masks */
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#define NINT 0x01 /* Pending Interrupt */
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#define STATUS 0x06 /* Highest Priority Pending Interrupt */
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#define NINT_P 0x00
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#define STATUS_P0 0x01
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#define STATUS_P1 0x02
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/* UARTx_GCTL Masks */
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#define UCEN 0x01 /* Enable UARTx Clocks */
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#define IREN 0x02 /* Enable IrDA Mode */
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#define TPOLC 0x04 /* IrDA TX Polarity Change */
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#define RPOLC 0x08 /* IrDA RX Polarity Change */
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#define FPE 0x10 /* Force Parity Error On Transmit */
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#define FFE 0x20 /* Force Framing Error On Transmit */
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#define UCEN_P 0x00
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#define IREN_P 0x01
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#define TPOLC_P 0x02
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#define RPOLC_P 0x03
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#define FPE_P 0x04
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#define FFE_P 0x05
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#endif
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