mirror of
https://github.com/AsahiLinux/u-boot
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361 lines
8.6 KiB
Text
361 lines
8.6 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* SoM: https://www.ti.com/lit/zip/sprr439
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*
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* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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#include "k3-j721s2.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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memory@80000000 {
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device_type = "memory";
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/* 16 GB RAM */
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reg = <0x00 0x80000000 0x00 0x80000000>,
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<0x08 0x80000000 0x03 0x80000000>;
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};
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/* Reserving memory regions still pending */
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reserved_memory: reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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secure_ddr: optee@9e800000 {
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reg = <0x00 0x9e800000 0x00 0x01800000>;
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alignment = <0x1000>;
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no-map;
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};
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mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa0000000 0x00 0x100000>;
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no-map;
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};
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mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa0100000 0x00 0xf00000>;
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no-map;
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};
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mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa1000000 0x00 0x100000>;
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no-map;
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};
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mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa1100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa2000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa2100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa3000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa3100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa4000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa4100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa5000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa5100000 0x00 0xf00000>;
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no-map;
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};
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c71_0_dma_memory_region: c71-dma-memory@a6000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa6000000 0x00 0x100000>;
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no-map;
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};
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c71_0_memory_region: c71-memory@a6100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa6100000 0x00 0xf00000>;
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no-map;
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};
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c71_1_dma_memory_region: c71-dma-memory@a7000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa7000000 0x00 0x100000>;
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no-map;
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};
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c71_1_memory_region: c71-memory@a7100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa7100000 0x00 0xf00000>;
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no-map;
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};
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rtos_ipc_memory_region: ipc-memories@a8000000 {
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reg = <0x00 0xa8000000 0x00 0x01c00000>;
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alignment = <0x1000>;
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no-map;
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};
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};
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mux0: mux-controller {
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compatible = "gpio-mux";
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#mux-state-cells = <1>;
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mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>;
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};
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mux1: mux-controller {
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compatible = "gpio-mux";
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#mux-state-cells = <1>;
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mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>;
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};
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transceiver0: can-phy0 {
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/* standby pin has been grounded by default */
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compatible = "ti,tcan1042";
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#phy-cells = <0>;
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max-bitrate = <5000000>;
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};
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};
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&wkup_pmx0 {
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mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
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pinctrl-single,pins = <
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J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */
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J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */
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J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */
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J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */
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J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */
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J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */
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J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */
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J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */
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J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */
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J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */
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J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
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J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */
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>;
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};
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};
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&wkup_pmx2 {
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wkup_i2c0_pins_default: wkup-i2c0-default-pins {
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pinctrl-single,pins = <
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J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */
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J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */
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>;
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};
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};
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&main_pmx0 {
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main_i2c0_pins_default: main-i2c0-default-pins {
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pinctrl-single,pins = <
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J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */
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J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */
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>;
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};
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main_mcan16_pins_default: main-mcan16-default-pins {
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pinctrl-single,pins = <
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J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */
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J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */
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>;
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};
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};
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&wkup_i2c0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&wkup_i2c0_pins_default>;
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clock-frequency = <400000>;
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eeprom@50 {
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/* CAV24C256WE-GT3 */
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compatible = "atmel,24c256";
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reg = <0x50>;
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};
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};
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&main_i2c0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&main_i2c0_pins_default>;
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clock-frequency = <400000>;
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exp_som: gpio@21 {
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compatible = "ti,tca6408";
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reg = <0x21>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
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"CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
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"GPIO_RGMII1_RST", "GPIO_eDP_ENABLE",
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"GPIO_LIN_EN", "CAN_STB";
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};
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};
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&main_mcan16 {
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status = "okay";
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pinctrl-0 = <&main_mcan16_pins_default>;
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pinctrl-names = "default";
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phys = <&transceiver0>;
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};
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&ospi0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0x0>;
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spi-tx-bus-width = <8>;
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spi-rx-bus-width = <8>;
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spi-max-frequency = <25000000>;
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cdns,tshsl-ns = <60>;
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cdns,tsd2d-ns = <60>;
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cdns,tchsh-ns = <60>;
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cdns,tslch-ns = <60>;
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cdns,read-delay = <4>;
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};
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};
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&mailbox0_cluster0 {
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status = "okay";
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interrupts = <436>;
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mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
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ti,mbox-rx = <0 0 0>;
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ti,mbox-tx = <1 0 0>;
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};
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mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
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ti,mbox-rx = <2 0 0>;
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ti,mbox-tx = <3 0 0>;
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};
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};
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&mailbox0_cluster1 {
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status = "okay";
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interrupts = <432>;
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mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
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ti,mbox-rx = <0 0 0>;
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ti,mbox-tx = <1 0 0>;
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};
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mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
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ti,mbox-rx = <2 0 0>;
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ti,mbox-tx = <3 0 0>;
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};
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};
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&mailbox0_cluster2 {
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status = "okay";
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interrupts = <428>;
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mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
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ti,mbox-rx = <0 0 0>;
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ti,mbox-tx = <1 0 0>;
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};
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mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
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ti,mbox-rx = <2 0 0>;
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ti,mbox-tx = <3 0 0>;
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};
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};
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&mailbox0_cluster4 {
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status = "okay";
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interrupts = <420>;
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mbox_c71_0: mbox-c71-0 {
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ti,mbox-rx = <0 0 0>;
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ti,mbox-tx = <1 0 0>;
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};
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mbox_c71_1: mbox-c71-1 {
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ti,mbox-rx = <2 0 0>;
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ti,mbox-tx = <3 0 0>;
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};
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};
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&mcu_r5fss0_core0 {
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mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
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memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
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<&mcu_r5fss0_core0_memory_region>;
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};
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&mcu_r5fss0_core1 {
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mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
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memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
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<&mcu_r5fss0_core1_memory_region>;
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};
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&main_r5fss0_core0 {
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mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
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memory-region = <&main_r5fss0_core0_dma_memory_region>,
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<&main_r5fss0_core0_memory_region>;
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};
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&main_r5fss0_core1 {
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mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
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memory-region = <&main_r5fss0_core1_dma_memory_region>,
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<&main_r5fss0_core1_memory_region>;
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};
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&main_r5fss1_core0 {
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mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
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memory-region = <&main_r5fss1_core0_dma_memory_region>,
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<&main_r5fss1_core0_memory_region>;
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};
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&main_r5fss1_core1 {
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mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
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memory-region = <&main_r5fss1_core1_dma_memory_region>,
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<&main_r5fss1_core1_memory_region>;
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};
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&c71_0 {
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status = "okay";
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mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
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memory-region = <&c71_0_dma_memory_region>,
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<&c71_0_memory_region>;
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};
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&c71_1 {
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status = "okay";
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mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>;
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memory-region = <&c71_1_dma_memory_region>,
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<&c71_1_memory_region>;
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};
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