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54e1aa236f
Add support for the Variscite VAR-SOM-IMX93 evaluation kit. The SoM consists of an NXP iMX93 dual A55 CPU. The SoM is mounted on a Variscite Symphony SBC. Signed-off-by: Mathieu Othacehe <m.othacehe@gmail.com>
111 lines
2.8 KiB
Text
111 lines
2.8 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2022 NXP
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* Copyright 2023 Variscite Ltd.
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*/
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/dts-v1/;
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#include "imx93.dtsi"
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/{
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model = "Variscite VAR-SOM-MX93 module";
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compatible = "variscite,var-som-mx93", "fsl,imx93";
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mmc_pwrseq: mmc-pwrseq {
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compatible = "mmc-pwrseq-simple";
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post-power-on-delay-ms = <100>;
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power-off-delay-us = <10000>;
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reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
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<&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
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};
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reg_eqos_phy: regulator-eqos-phy {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_eqos_phy>;
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regulator-name = "eth_phy_pwr";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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startup-delay-us = <100000>;
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regulator-always-on;
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};
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};
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&eqos {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_eqos>;
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phy-mode = "rgmii";
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phy-handle = <ðphy0>;
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phy-supply = <®_eqos_phy>;
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status = "okay";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <1000000>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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eee-broken-1000t;
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};
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};
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};
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&iomuxc {
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pinctrl_eqos: eqosgrp {
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fsl,pins = <
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MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
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MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
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MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
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MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
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MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
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MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
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MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe
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MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
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MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
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MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
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MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
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MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
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MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
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MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
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>;
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};
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pinctrl_reg_eqos_phy: regeqosgrp {
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fsl,pins = <
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MX93_PAD_UART2_TXD__GPIO1_IO07 0x51e
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
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MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe
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MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
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MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
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MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
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MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
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MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
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MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
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MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
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MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
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MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
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>;
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};
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};
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/* eMMC */
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1>;
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pinctrl-2 = <&pinctrl_usdhc1>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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