mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 22:03:15 +00:00
21b30c237a
With DM enabled, there is no need for board code to initialize the Ethernet interfaces. The RTL8211FDI Ethernet PHYs have 25MHz oscillator, so there is no need to enable the RGMII TX clk output. Also, there is no need for describing the deprecated phy-reset FEC properties, nor passing reset properties to the EQOS interface in u-boot.dtsi. Remove all these unneeded pieces. Tested both Ethernet interfaces after these changes. Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
139 lines
1.3 KiB
Text
139 lines
1.3 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019, 2021 NXP
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*/
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#include "imx8mp-u-boot.dtsi"
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/ {
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdog1>;
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bootph-pre-ram;
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};
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};
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&pinctrl_i2c1 {
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bootph-all;
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};
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&pinctrl_pmic {
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bootph-all;
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};
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&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
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bootph-all;
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};
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&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
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bootph-all;
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};
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®_usdhc2_vmmc {
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u-boot,off-on-delay-us = <20000>;
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};
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®_usdhc2_vmmc {
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bootph-pre-ram;
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};
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&pinctrl_uart2 {
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bootph-pre-ram;
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};
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&pinctrl_usdhc2_gpio {
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bootph-pre-ram;
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};
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&pinctrl_usdhc2 {
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bootph-pre-ram;
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};
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&pinctrl_usdhc3 {
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bootph-pre-ram;
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};
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&pinctrl_wdog {
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bootph-pre-ram;
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};
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&gpio1 {
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bootph-pre-ram;
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};
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&gpio2 {
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bootph-pre-ram;
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};
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&gpio3 {
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bootph-pre-ram;
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};
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&gpio4 {
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bootph-pre-ram;
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};
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&gpio5 {
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bootph-pre-ram;
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};
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&uart2 {
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bootph-pre-ram;
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};
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&i2c1 {
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bootph-all;
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};
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&i2c2 {
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bootph-pre-ram;
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};
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&i2c3 {
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bootph-pre-ram;
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};
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&i2c4 {
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bootph-pre-ram;
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};
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&i2c5 {
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bootph-pre-ram;
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};
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&i2c6 {
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bootph-pre-ram;
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};
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&usb_dwc3_0 {
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dr_mode = "peripheral";
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status = "okay";
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};
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&usb3_0 {
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status = "okay";
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};
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&usb3_phy0 {
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status = "okay";
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};
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&usdhc1 {
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bootph-pre-ram;
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};
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&usdhc2 {
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bootph-pre-ram;
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sd-uhs-sdr104;
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sd-uhs-ddr50;
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};
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&usdhc3 {
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bootph-pre-ram;
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mmc-hs400-1_8v;
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mmc-hs400-enhanced-strobe;
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};
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&wdog1 {
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bootph-pre-ram;
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};
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