mirror of
https://github.com/AsahiLinux/u-boot
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371 lines
9.3 KiB
C
371 lines
9.3 KiB
C
/*
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* (C) Copyright 2001
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* Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
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* and
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* Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <common.h>
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#include "w7o.h"
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#include <asm/processor.h>
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#include <linux/compiler.h>
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#include "errors.h"
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static void
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fpga_img_write(unsigned long *src, unsigned long len, unsigned short *daddr)
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{
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unsigned long i;
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volatile unsigned long val;
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volatile unsigned short *dest = daddr; /* volatile-bypass optimizer */
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for (i = 0; i < len; i++, src++) {
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val = *src;
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*dest = (unsigned short) ((val & 0xff000000L) >> 16);
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*dest = (unsigned short) ((val & 0x00ff0000L) >> 8);
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*dest = (unsigned short) (val & 0x0000ff00L);
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*dest = (unsigned short) ((val & 0x000000ffL) << 8);
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}
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/* Terminate programming with 4 C clocks */
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dest = daddr;
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val = *(unsigned short *) dest;
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val = *(unsigned short *) dest;
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val = *(unsigned short *) dest;
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val = *(unsigned short *) dest;
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}
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int
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fpgaDownload(unsigned char *saddr, unsigned long size, unsigned short *daddr)
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{
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int i; /* index, intr disable flag */
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int start; /* timer */
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unsigned long greg, grego; /* GPIO & output register */
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unsigned long length; /* image size in words */
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unsigned long *source; /* image source addr */
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unsigned short *dest; /* destination FPGA addr */
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volatile unsigned short *ndest; /* temp dest FPGA addr */
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unsigned long cnfg = GPIO_XCV_CNFG; /* FPGA CNFG */
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unsigned long eirq = GPIO_XCV_IRQ;
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int retval = -1; /* Function return value */
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__maybe_unused volatile unsigned short val; /* temp val */
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/* Setup some basic values */
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length = (size / 4) + 1; /* size in words, rounding UP
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is OK */
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source = (unsigned long *) saddr;
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dest = (unsigned short *) daddr;
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/* Get DCR output register */
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grego = in32(PPC405GP_GPIO0_OR);
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/* Reset FPGA */
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grego &= ~GPIO_XCV_PROG; /* PROG line low */
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out32(PPC405GP_GPIO0_OR, grego);
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/* Setup timeout timer */
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start = get_timer(0);
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/* Wait for FPGA init line to go low */
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while (in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT) {
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/* Check for timeout - 100us max, so use 3ms */
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if (get_timer(start) > 3) {
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printf(" failed to start init.\n");
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log_warn(ERR_XINIT0); /* Don't halt */
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/* Reset line stays low */
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goto done; /* I like gotos... */
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}
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}
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/* Unreset FPGA */
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grego |= GPIO_XCV_PROG; /* PROG line high */
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out32(PPC405GP_GPIO0_OR, grego);
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/* Wait for FPGA end of init period = init line go hi */
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while (!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT)) {
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/* Check for timeout */
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if (get_timer(start) > 3) {
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printf(" failed to exit init.\n");
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log_warn(ERR_XINIT1);
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/* Reset FPGA */
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grego &= ~GPIO_XCV_PROG; /* PROG line low */
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out32(PPC405GP_GPIO0_OR, grego);
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goto done;
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}
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}
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/* Now program FPGA ... */
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ndest = dest;
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for (i = 0; i < CONFIG_NUM_FPGAS; i++) {
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/* Toggle IRQ/GPIO */
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greg = mfdcr(CPC0_CR0); /* get chip ctrl register */
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greg |= eirq; /* toggle irq/gpio */
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mtdcr(CPC0_CR0, greg); /* ... just do it */
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/* turn on open drain for CNFG */
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greg = in32(PPC405GP_GPIO0_ODR); /* get open drain register */
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greg |= cnfg; /* CNFG open drain */
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out32(PPC405GP_GPIO0_ODR, greg); /* .. just do it */
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/* Turn output enable on for CNFG */
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greg = in32(PPC405GP_GPIO0_TCR); /* get tristate register */
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greg |= cnfg; /* CNFG tristate inactive */
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out32(PPC405GP_GPIO0_TCR, greg); /* ... just do it */
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/* Setup FPGA for programming */
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grego &= ~cnfg; /* CONFIG line low */
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out32(PPC405GP_GPIO0_OR, grego);
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/*
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* Program the FPGA
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*/
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printf("\n destination: 0x%lx ", (unsigned long) ndest);
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fpga_img_write(source, length, (unsigned short *) ndest);
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/* Done programming */
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grego |= cnfg; /* CONFIG line high */
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out32(PPC405GP_GPIO0_OR, grego);
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/* Turn output enable OFF for CNFG */
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greg = in32(PPC405GP_GPIO0_TCR); /* get tristate register */
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greg &= ~cnfg; /* CNFG tristate inactive */
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out32(PPC405GP_GPIO0_TCR, greg); /* ... just do it */
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/* Toggle IRQ/GPIO */
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greg = mfdcr(CPC0_CR0); /* get chip ctrl register */
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greg &= ~eirq; /* toggle irq/gpio */
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mtdcr(CPC0_CR0, greg); /* ... just do it */
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/* XXX - Next FPGA addr */
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ndest = (unsigned short *) ((char *) ndest + 0x00100000L);
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cnfg >>= 1; /* XXX - Next */
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eirq >>= 1;
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}
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/* Terminate programming with 4 C clocks */
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ndest = dest;
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for (i = 0; i < CONFIG_NUM_FPGAS; i++) {
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val = *ndest;
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val = *ndest;
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val = *ndest;
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val = *ndest;
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ndest = (unsigned short *) ((char *) ndest + 0x00100000L);
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}
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/* Setup timer */
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start = get_timer(0);
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/* Wait for FPGA end of programming period = Test DONE low */
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while (!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_DONE)) {
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/* Check for timeout */
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if (get_timer(start) > 3) {
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printf(" done failed to come high.\n");
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log_warn(ERR_XDONE1);
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/* Reset FPGA */
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grego &= ~GPIO_XCV_PROG; /* PROG line low */
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out32(PPC405GP_GPIO0_OR, grego);
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goto done;
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}
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}
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printf("\n FPGA load succeeded\n");
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retval = 0; /* Program OK */
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done:
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return retval;
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}
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/* FPGA image is stored in flash */
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extern flash_info_t flash_info[];
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int init_fpga(void)
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{
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unsigned int i, j, ptr; /* General purpose */
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unsigned char bufchar; /* General purpose character */
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unsigned char *buf; /* Start of image pointer */
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unsigned long len; /* Length of image */
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unsigned char *fn_buf; /* Start of filename string */
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unsigned int fn_len; /* Length of filename string */
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unsigned char *xcv_buf; /* Pointer to start of image */
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unsigned long xcv_len; /* Length of image */
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unsigned long crc; /* 30bit crc in image */
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unsigned long calc_crc; /* Calc'd 30bit crc */
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int retval = -1;
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/* Tell the world what we are doing */
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printf("FPGA: ");
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/*
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* Get address of first sector where the FPGA
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* image is stored.
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*/
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buf = (unsigned char *) flash_info[1].start[0];
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/*
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* Get the stored image's CRC & length.
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*/
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crc = *(unsigned long *) (buf + 4); /* CRC is first long word */
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len = *(unsigned long *) (buf + 8); /* Image len is next long */
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/* Pedantic */
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if ((len < 0x133A4) || (len > 0x80000))
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goto bad_image;
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/*
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* Get the file name pointer and length.
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* filename length is next short
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*/
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fn_len = (*(unsigned short *) (buf + 12) & 0xff);
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fn_buf = buf + 14;
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/*
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* Get the FPGA image pointer and length length.
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*/
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xcv_buf = fn_buf + fn_len; /* pointer to fpga image */
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xcv_len = len - 14 - fn_len; /* fpga image length */
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/* Check for uninitialized FLASH */
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if ((strncmp((char *) buf, "w7o", 3) != 0) || (len > 0x0007ffffL)
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|| (len == 0))
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goto bad_image;
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/*
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* Calculate and Check the image's CRC.
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*/
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calc_crc = crc32(0, xcv_buf, xcv_len);
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if (crc != calc_crc) {
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printf("\nfailed - bad CRC\n");
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goto done;
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}
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/* Output the file name */
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printf("file name : ");
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for (i = 0; i < fn_len; i++) {
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bufchar = fn_buf[+i];
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if (bufchar < ' ' || bufchar > '~')
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bufchar = '.';
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putc(bufchar);
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}
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/*
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* find rest of display data
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*/
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ptr = 15; /* Offset to ncd filename
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length in fpga image */
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j = xcv_buf[ptr]; /* Get len of ncd filename */
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if (j > 32)
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goto bad_image;
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ptr = ptr + j + 3; /* skip ncd filename string +
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3 bytes more bytes */
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/*
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* output target device string
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*/
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j = xcv_buf[ptr++] - 1; /* len of targ str less term */
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if (j > 32)
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goto bad_image;
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printf("\n target : ");
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for (i = 0; i < j; i++) {
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bufchar = (xcv_buf[ptr++]);
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if (bufchar < ' ' || bufchar > '~')
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bufchar = '.';
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putc(bufchar);
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}
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/*
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* output compilation date string and time string
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*/
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ptr += 3; /* skip 2 bytes */
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printf("\n synth time : ");
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j = (xcv_buf[ptr++] - 1); /* len of date str less term */
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if (j > 32)
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goto bad_image;
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for (i = 0; i < j; i++) {
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bufchar = (xcv_buf[ptr++]);
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if (bufchar < ' ' || bufchar > '~')
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bufchar = '.';
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putc(bufchar);
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}
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ptr += 3; /* Skip 2 bytes */
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printf(" - ");
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j = (xcv_buf[ptr++] - 1); /* slen = targ dev str len */
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if (j > 32)
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goto bad_image;
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for (i = 0; i < j; i++) {
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bufchar = (xcv_buf[ptr++]);
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if (bufchar < ' ' || bufchar > '~')
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bufchar = '.';
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putc(bufchar);
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}
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/*
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* output crc and length strings
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*/
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printf("\n len & crc : 0x%lx 0x%lx", len, crc);
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/*
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* Program the FPGA.
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*/
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retval = fpgaDownload((unsigned char *) xcv_buf, xcv_len,
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(unsigned short *) 0xfd000000L);
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return retval;
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bad_image:
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printf("\n BAD FPGA image format @ %lx\n",
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flash_info[1].start[0]);
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log_warn(ERR_XIMAGE);
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done:
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return retval;
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}
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void test_fpga(unsigned short *daddr)
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{
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int i;
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volatile unsigned short *ndest = daddr;
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for (i = 0; i < CONFIG_NUM_FPGAS; i++) {
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#if defined(CONFIG_W7OLMG)
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ndest[0x7e] = 0x55aa;
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if (ndest[0x7e] != 0x55aa)
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log_warn(ERR_XRW1 + i);
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ndest[0x7e] = 0xaa55;
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if (ndest[0x7e] != 0xaa55)
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log_warn(ERR_XRW1 + i);
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ndest[0x7e] = 0xc318;
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if (ndest[0x7e] != 0xc318)
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log_warn(ERR_XRW1 + i);
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#elif defined(CONFIG_W7OLMC)
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ndest[0x800] = 0x55aa;
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ndest[0x801] = 0xaa55;
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ndest[0x802] = 0xc318;
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ndest[0x4800] = 0x55aa;
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ndest[0x4801] = 0xaa55;
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ndest[0x4802] = 0xc318;
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if ((ndest[0x800] != 0x55aa) ||
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(ndest[0x801] != 0xaa55) || (ndest[0x802] != 0xc318))
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log_warn(ERR_XRW1 + (2 * i)); /* Auto gen error code */
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if ((ndest[0x4800] != 0x55aa) ||
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(ndest[0x4801] != 0xaa55) || (ndest[0x4802] != 0xc318))
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log_warn(ERR_XRW2 + (2 * i)); /* Auto gen error code */
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#else
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#error "Unknown W7O board configuration"
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#endif
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}
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printf(" FPGA ready\n");
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return;
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}
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