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a78cd86132
As part of testing booting Linux kernels on Rockchip devices, it was discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for some cases incomplete isb definitions. This was causing a failure to boot of the Linux kernel. In order to solve this problem as well as cover any corner cases that we may also have had a number of changes are made in order to consolidate things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb definitions. This however introduces another complexity. Due to needing to build SPL for 32bit tegra with -march=armv4 we need to borrow the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add a comment about it. Now that we can always know what the target CPU is capable off we can get always do the correct thing for the barrier. The final part of this is that need to be consistent everywhere and call isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the function names in others. Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Sandy Patterson <apatterson@sightlogix.com> Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reported-by: Sandy Patterson <apatterson@sightlogix.com> Signed-off-by: Tom Rini <trini@konsulko.com>
214 lines
4.8 KiB
C
214 lines
4.8 KiB
C
/*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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* Aneesh V <aneesh@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/types.h>
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#include <common.h>
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#include <asm/armv7.h>
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#include <asm/utils.h>
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#define ARMV7_DCACHE_INVAL_RANGE 1
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#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 2
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#ifndef CONFIG_SYS_DCACHE_OFF
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/* Asm functions from cache_v7_asm.S */
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void v7_flush_dcache_all(void);
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void v7_invalidate_dcache_all(void);
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static u32 get_ccsidr(void)
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{
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u32 ccsidr;
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/* Read current CP15 Cache Size ID Register */
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asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr));
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return ccsidr;
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}
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static void v7_dcache_clean_inval_range(u32 start, u32 stop, u32 line_len)
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{
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u32 mva;
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/* Align start to cache line boundary */
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start &= ~(line_len - 1);
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for (mva = start; mva < stop; mva = mva + line_len) {
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/* DCCIMVAC - Clean & Invalidate data cache by MVA to PoC */
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asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva));
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}
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}
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static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len)
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{
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u32 mva;
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if (!check_cache_range(start, stop))
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return;
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for (mva = start; mva < stop; mva = mva + line_len) {
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/* DCIMVAC - Invalidate data cache by MVA to PoC */
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asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva));
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}
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}
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static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
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{
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u32 line_len, ccsidr;
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ccsidr = get_ccsidr();
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line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >>
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CCSIDR_LINE_SIZE_OFFSET) + 2;
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/* Converting from words to bytes */
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line_len += 2;
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/* converting from log2(linelen) to linelen */
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line_len = 1 << line_len;
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switch (range_op) {
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case ARMV7_DCACHE_CLEAN_INVAL_RANGE:
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v7_dcache_clean_inval_range(start, stop, line_len);
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break;
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case ARMV7_DCACHE_INVAL_RANGE:
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v7_dcache_inval_range(start, stop, line_len);
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break;
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}
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/* DSB to make sure the operation is complete */
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dsb();
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}
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/* Invalidate TLB */
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static void v7_inval_tlb(void)
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{
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/* Invalidate entire unified TLB */
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asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
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/* Invalidate entire data TLB */
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asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0));
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/* Invalidate entire instruction TLB */
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asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
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/* Full system DSB - make sure that the invalidation is complete */
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dsb();
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/* Full system ISB - make sure the instruction stream sees it */
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isb();
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}
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void invalidate_dcache_all(void)
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{
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v7_invalidate_dcache_all();
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v7_outer_cache_inval_all();
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}
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/*
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* Performs a clean & invalidation of the entire data cache
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* at all levels
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*/
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void flush_dcache_all(void)
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{
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v7_flush_dcache_all();
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v7_outer_cache_flush_all();
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}
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/*
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* Invalidates range in all levels of D-cache/unified cache used:
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* Affects the range [start, stop - 1]
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*/
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void invalidate_dcache_range(unsigned long start, unsigned long stop)
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{
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check_cache_range(start, stop);
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v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE);
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v7_outer_cache_inval_range(start, stop);
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}
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/*
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* Flush range(clean & invalidate) from all levels of D-cache/unified
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* cache used:
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* Affects the range [start, stop - 1]
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*/
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void flush_dcache_range(unsigned long start, unsigned long stop)
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{
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check_cache_range(start, stop);
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v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE);
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v7_outer_cache_flush_range(start, stop);
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}
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void arm_init_before_mmu(void)
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{
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v7_outer_cache_enable();
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invalidate_dcache_all();
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v7_inval_tlb();
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}
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void mmu_page_table_flush(unsigned long start, unsigned long stop)
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{
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flush_dcache_range(start, stop);
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v7_inval_tlb();
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}
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#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
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void invalidate_dcache_all(void)
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{
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}
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void flush_dcache_all(void)
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{
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}
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void invalidate_dcache_range(unsigned long start, unsigned long stop)
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{
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}
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void flush_dcache_range(unsigned long start, unsigned long stop)
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{
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}
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void arm_init_before_mmu(void)
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{
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}
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void mmu_page_table_flush(unsigned long start, unsigned long stop)
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{
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}
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void arm_init_domains(void)
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{
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}
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#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
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#ifndef CONFIG_SYS_ICACHE_OFF
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/* Invalidate entire I-cache and branch predictor array */
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void invalidate_icache_all(void)
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{
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/*
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* Invalidate all instruction caches to PoU.
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* Also flushes branch target cache.
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*/
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asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
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/* Invalidate entire branch predictor array */
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asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
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/* Full system DSB - make sure that the invalidation is complete */
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dsb();
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/* ISB - make sure the instruction stream sees it */
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isb();
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}
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#else
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void invalidate_icache_all(void)
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{
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}
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#endif
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/* Stub implementations for outer cache operations */
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__weak void v7_outer_cache_enable(void) {}
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__weak void v7_outer_cache_disable(void) {}
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__weak void v7_outer_cache_flush_all(void) {}
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__weak void v7_outer_cache_inval_all(void) {}
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__weak void v7_outer_cache_flush_range(u32 start, u32 end) {}
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__weak void v7_outer_cache_inval_range(u32 start, u32 end) {}
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