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93a0ea501e
This patch moves mx31 to the common timer functions added in commit
8dfafdd - Introduce common timer functions <Rob Herring>
The (removed) mx31 timer code (specifically __udelay()) could deadlock at
the 32-bit boundary of get_ticks(). get_ticks() returned a 32-bit value
cast up to a 64-bit value. If get_ticks() + tmo in __udelay() crossed
the 32-bit boundary, the while condition became unconditionally true and
locks the processor. Rather than patch the specific mx31 issues, simply
move everything over to the common code.
Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Helmut Raiger <helmut.raiger@hale.at>
47 lines
1.1 KiB
C
47 lines
1.1 KiB
C
/*
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* (C) Copyright 2007
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* Sascha Hauer, Pengutronix
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/io.h>
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#define TIMER_BASE 0x53f90000 /* General purpose timer 1 */
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/* General purpose timers registers */
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#define GPTCR __REG(TIMER_BASE) /* Control register */
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#define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */
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#define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */
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#define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */
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/* General purpose timers bitfields */
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#define GPTCR_SWR (1 << 15) /* Software reset */
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#define GPTCR_FRR (1 << 9) /* Freerun / restart */
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#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
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#define GPTCR_TEN 1 /* Timer enable */
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DECLARE_GLOBAL_DATA_PTR;
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/* The 32768Hz 32-bit timer overruns in 131072 seconds */
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int timer_init(void)
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{
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int i;
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/* setup GP Timer 1 */
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GPTCR = GPTCR_SWR;
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for (i = 0; i < 100; i++)
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GPTCR = 0; /* We have no udelay by now */
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GPTPR = 0; /* 32Khz */
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/* Freerun Mode, PERCLK1 input */
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GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
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return 0;
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}
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unsigned long timer_read_counter(void)
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{
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return GPTCNT;
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}
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