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https://github.com/AsahiLinux/u-boot
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1e6ad55c05
When SoC first boots up, we should invalidate the cache but not flush it. We can use the same function for invalid and flush mostly, with a wrapper. Invalidating large cache can ben slow on emulator, so we postpone doing so until I-cache is enabled, and before enabling D-cache. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn>
236 lines
4.4 KiB
C
236 lines
4.4 KiB
C
/*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/system.h>
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#include <asm/armv8/mmu.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_SYS_DCACHE_OFF
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static void set_pgtable_section(u64 section, u64 memory_type)
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{
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u64 *page_table = (u64 *)gd->arch.tlb_addr;
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u64 value;
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value = (section << SECTION_SHIFT) | PMD_TYPE_SECT | PMD_SECT_AF;
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value |= PMD_ATTRINDX(memory_type);
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page_table[section] = value;
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}
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/* to activate the MMU we need to set up virtual memory */
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static void mmu_setup(void)
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{
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int i, j, el;
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bd_t *bd = gd->bd;
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/* Setup an identity-mapping for all spaces */
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for (i = 0; i < (PGTABLE_SIZE >> 3); i++)
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set_pgtable_section(i, MT_DEVICE_NGNRNE);
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/* Setup an identity-mapping for all RAM space */
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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ulong start = bd->bi_dram[i].start;
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ulong end = bd->bi_dram[i].start + bd->bi_dram[i].size;
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for (j = start >> SECTION_SHIFT;
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j < end >> SECTION_SHIFT; j++) {
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set_pgtable_section(j, MT_NORMAL);
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}
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}
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/* load TTBR0 */
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el = current_el();
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if (el == 1) {
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asm volatile("msr ttbr0_el1, %0"
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: : "r" (gd->arch.tlb_addr) : "memory");
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asm volatile("msr tcr_el1, %0"
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: : "r" (TCR_FLAGS | TCR_EL1_IPS_BITS)
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: "memory");
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asm volatile("msr mair_el1, %0"
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: : "r" (MEMORY_ATTRIBUTES) : "memory");
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} else if (el == 2) {
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asm volatile("msr ttbr0_el2, %0"
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: : "r" (gd->arch.tlb_addr) : "memory");
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asm volatile("msr tcr_el2, %0"
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: : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS)
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: "memory");
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asm volatile("msr mair_el2, %0"
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: : "r" (MEMORY_ATTRIBUTES) : "memory");
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} else {
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asm volatile("msr ttbr0_el3, %0"
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: : "r" (gd->arch.tlb_addr) : "memory");
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asm volatile("msr tcr_el3, %0"
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: : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS)
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: "memory");
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asm volatile("msr mair_el3, %0"
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: : "r" (MEMORY_ATTRIBUTES) : "memory");
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}
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/* enable the mmu */
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set_sctlr(get_sctlr() | CR_M);
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}
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/*
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* Performs a invalidation of the entire data cache at all levels
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*/
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void invalidate_dcache_all(void)
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{
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__asm_invalidate_dcache_all();
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}
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/*
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* Performs a clean & invalidation of the entire data cache at all levels
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*/
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void flush_dcache_all(void)
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{
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__asm_flush_dcache_all();
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}
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/*
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* Invalidates range in all levels of D-cache/unified cache
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*/
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void invalidate_dcache_range(unsigned long start, unsigned long stop)
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{
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__asm_flush_dcache_range(start, stop);
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}
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/*
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* Flush range(clean & invalidate) from all levels of D-cache/unified cache
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*/
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void flush_dcache_range(unsigned long start, unsigned long stop)
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{
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__asm_flush_dcache_range(start, stop);
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}
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void dcache_enable(void)
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{
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/* The data cache is not active unless the mmu is enabled */
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if (!(get_sctlr() & CR_M)) {
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invalidate_dcache_all();
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__asm_invalidate_tlb_all();
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mmu_setup();
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}
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set_sctlr(get_sctlr() | CR_C);
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}
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void dcache_disable(void)
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{
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uint32_t sctlr;
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sctlr = get_sctlr();
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/* if cache isn't enabled no need to disable */
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if (!(sctlr & CR_C))
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return;
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set_sctlr(sctlr & ~(CR_C|CR_M));
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flush_dcache_all();
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__asm_invalidate_tlb_all();
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}
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int dcache_status(void)
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{
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return (get_sctlr() & CR_C) != 0;
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}
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#else /* CONFIG_SYS_DCACHE_OFF */
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void invalidate_dcache_all(void)
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{
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}
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void flush_dcache_all(void)
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{
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}
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void invalidate_dcache_range(unsigned long start, unsigned long stop)
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{
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}
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void flush_dcache_range(unsigned long start, unsigned long stop)
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{
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}
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void dcache_enable(void)
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{
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}
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void dcache_disable(void)
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{
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}
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int dcache_status(void)
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{
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return 0;
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}
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#endif /* CONFIG_SYS_DCACHE_OFF */
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#ifndef CONFIG_SYS_ICACHE_OFF
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void icache_enable(void)
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{
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__asm_invalidate_icache_all();
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set_sctlr(get_sctlr() | CR_I);
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}
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void icache_disable(void)
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{
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set_sctlr(get_sctlr() & ~CR_I);
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}
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int icache_status(void)
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{
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return (get_sctlr() & CR_I) != 0;
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}
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void invalidate_icache_all(void)
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{
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__asm_invalidate_icache_all();
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}
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#else /* CONFIG_SYS_ICACHE_OFF */
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void icache_enable(void)
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{
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}
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void icache_disable(void)
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{
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}
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int icache_status(void)
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{
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return 0;
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}
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void invalidate_icache_all(void)
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{
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}
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#endif /* CONFIG_SYS_ICACHE_OFF */
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/*
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* Enable dCache & iCache, whether cache is actually enabled
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* depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF
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*/
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void enable_caches(void)
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{
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icache_enable();
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dcache_enable();
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}
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/*
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* Flush range from all levels of d-cache/unified-cache
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*/
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void flush_cache(unsigned long start, unsigned long size)
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{
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flush_dcache_range(start, start + size);
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}
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