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5614e71b49
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
71 lines
1.7 KiB
C
71 lines
1.7 KiB
C
/*
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* Copyright 2010 Freescale Semiconductor, Inc.
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* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
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* Timur Tabi <timur@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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unsigned int i;
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if (ctrl_num) {
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printf("Wrong parameter for controller number %d", ctrl_num);
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return;
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}
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if (!pdimm->n_ranks)
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return;
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/* set odt_rd_cfg and odt_wr_cfg. */
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
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popts->cs_local_opts[i].odt_rd_cfg = 0;
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popts->cs_local_opts[i].odt_wr_cfg = 1;
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}
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popts->clk_adjust = 5;
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popts->cpo_override = 0x1f;
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popts->write_data_delay = 2;
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popts->half_strength_driver_enable = 1;
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/* Per AN4039, enable ZQ calibration. */
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popts->zq_en = 1;
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}
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#ifdef CONFIG_SPD_EEPROM
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/*
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* we only have a "fake" SPD-EEPROM here, which has 16 bit addresses
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*/
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void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
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{
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int ret = i2c_read(i2c_address, 0, 2, (uchar *)spd,
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sizeof(generic_spd_eeprom_t));
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if (ret) {
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if (i2c_address ==
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#ifdef SPD_EEPROM_ADDRESS
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SPD_EEPROM_ADDRESS
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#elif defined(SPD_EEPROM_ADDRESS1)
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SPD_EEPROM_ADDRESS1
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#endif
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) {
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printf("DDR: failed to read SPD from address %u\n",
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i2c_address);
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} else {
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debug("DDR: failed to read SPD from address %u\n",
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i2c_address);
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}
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memset(spd, 0, sizeof(generic_spd_eeprom_t));
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}
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}
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#endif
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