u-boot/drivers/pch/pch-uclass.c
Bin Meng 79d4eb627c dm: pch: Add get_io_base op
On some newer chipset (eg: BayTrail), there is an IO base address
register on the PCH device which configures the base address of a
memory-mapped I/O controller.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:21 +08:00

74 lines
1.4 KiB
C

/*
* Copyright (c) 2015 Google, Inc
* Written by Simon Glass <sjg@chromium.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <pch.h>
#include <dm/root.h>
DECLARE_GLOBAL_DATA_PTR;
int pch_get_spi_base(struct udevice *dev, ulong *sbasep)
{
struct pch_ops *ops = pch_get_ops(dev);
*sbasep = 0;
if (!ops->get_spi_base)
return -ENOSYS;
return ops->get_spi_base(dev, sbasep);
}
int pch_set_spi_protect(struct udevice *dev, bool protect)
{
struct pch_ops *ops = pch_get_ops(dev);
if (!ops->set_spi_protect)
return -ENOSYS;
return ops->set_spi_protect(dev, protect);
}
int pch_get_gpio_base(struct udevice *dev, u32 *gbasep)
{
struct pch_ops *ops = pch_get_ops(dev);
*gbasep = 0;
if (!ops->get_gpio_base)
return -ENOSYS;
return ops->get_gpio_base(dev, gbasep);
}
int pch_get_io_base(struct udevice *dev, u32 *iobasep)
{
struct pch_ops *ops = pch_get_ops(dev);
*iobasep = 0;
if (!ops->get_io_base)
return -ENOSYS;
return ops->get_io_base(dev, iobasep);
}
static int pch_uclass_post_bind(struct udevice *bus)
{
/*
* Scan the device tree for devices
*
* Before relocation, only bind devices marked for pre-relocation
* use.
*/
return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
gd->flags & GD_FLG_RELOC ? false : true);
}
UCLASS_DRIVER(pch) = {
.id = UCLASS_PCH,
.name = "pch",
.post_bind = pch_uclass_post_bind,
};