mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 08:57:58 +00:00
8bde7f776c
- remove trailing white space, trailing empty lines, C++ comments, etc.
- split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)
* Patches by Kenneth Johansson, 25 Jun 2003:
- major rework of command structure
(work done mostly by Michal Cendrowski and Joakim Kristiansen)
135 lines
3.2 KiB
ArmAsm
135 lines
3.2 KiB
ArmAsm
/*
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* Memory Setup stuff - taken from blob memsetup.S
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*
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* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
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* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include "config.h"
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#include "version.h"
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/* some parameters for the board */
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MEM_BASE: .long 0xa0000000
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MEM_START: .long 0xc0000000
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#define MDCNFG 0x00
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#define MDCAS00 0x04 /* CAS waveform rotate reg 0 */
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#define MDCAS01 0x08 /* CAS waveform rotate reg 1 bank */
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#define MDCAS02 0x0C /* CAS waveform rotate reg 2 bank */
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#define MDREFR 0x1C /* DRAM refresh control reg */
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#define MDCAS20 0x20 /* CAS waveform rotate reg 0 bank */
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#define MDCAS21 0x24 /* CAS waveform rotate reg 1 bank */
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#define MDCAS22 0x28 /* CAS waveform rotate reg 2 bank */
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#define MECR 0x18 /* Expansion memory (PCMCIA) bus configuration register */
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#define MSC0 0x10 /* static memory control reg 0 */
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#define MSC1 0x14 /* static memory control reg 1 */
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#define MSC2 0x2C /* static memory control reg 2 */
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#define SMCNFG 0x30 /* SMROM configuration reg */
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mdcas00: .long 0x5555557F
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mdcas01: .long 0x55555555
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mdcas02: .long 0x55555555
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mdcas20: .long 0x5555557F
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mdcas21: .long 0x55555555
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mdcas22: .long 0x55555555
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mdcnfg: .long 0x0000B25C
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mdrefr: .long 0x007000C1
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mecr: .long 0x10841084
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msc0: .long 0x00004774
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msc1: .long 0x00000000
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msc2: .long 0x00000000
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smcnfg: .long 0x00000000
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/* setting up the memory */
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.globl memsetup
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memsetup:
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ldr r0, MEM_BASE
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/* Set up the DRAM */
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/* MDCAS00 */
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ldr r1, mdcas00
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str r1, [r0, #MDCAS00]
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/* MDCAS01 */
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ldr r1, mdcas01
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str r1, [r0, #MDCAS01]
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/* MDCAS02 */
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ldr r1, mdcas02
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str r1, [r0, #MDCAS02]
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/* MDCAS20 */
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ldr r1, mdcas20
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str r1, [r0, #MDCAS20]
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/* MDCAS21 */
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ldr r1, mdcas21
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str r1, [r0, #MDCAS21]
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/* MDCAS22 */
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ldr r1, mdcas22
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str r1, [r0, #MDCAS22]
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/* MDREFR */
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ldr r1, mdrefr
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str r1, [r0, #MDREFR]
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/* Set up PCMCIA space */
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ldr r1, mecr
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str r1, [r0, #MECR]
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/* Setup the flash memory and other */
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ldr r1, msc0
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str r1, [r0, #MSC0]
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ldr r1, msc1
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str r1, [r0, #MSC1]
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ldr r1, msc2
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str r1, [r0, #MSC2]
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ldr r1, smcnfg
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str r1, [r0, #SMCNFG]
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/* MDCNFG */
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ldr r1, mdcnfg
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bic r1, r1, #0x00000001
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str r1, [r0, #MDCNFG]
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/* Load something to activate bank */
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ldr r2, MEM_START
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.rept 8
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ldr r1, [r2]
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.endr
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/* MDCNFG */
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ldr r1, mdcnfg
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orr r1, r1, #0x00000001
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str r1, [r0, #MDCNFG]
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/* everything is fine now */
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mov pc, lr
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