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2e0e5271aa
Currently we do 1) Index_Store_Tag_I, 2) Fill and 3) Index_Store_Tag_I again per a loop for I-cache initialization. But according to 'See MIPS Run', we're encouraged to use three separate loops rather than combining them *for both I- and D-cache*. This patch tries to fix this. In accordance with fixing above, mips_init_[id]cache are separated from mips_cache_reset(), and rewrite cache loops are completely rewritten with useful macros. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> |
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.. | ||
asc_serial.c | ||
asc_serial.h | ||
au1x00_eth.c | ||
au1x00_serial.c | ||
au1x00_usb_ohci.c | ||
au1x00_usb_ohci.h | ||
cache.S | ||
config.mk | ||
cpu.c | ||
incaip_clock.c | ||
incaip_wdt.S | ||
interrupts.c | ||
Makefile | ||
start.S |