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f56348af5d
The purpose of this patch is to prepare for adding the OMAP4 architecture, which is Cortex A9 Cortex A8 and A9 both belong to the armv7 architecture, hence the name change. The two architectures are similar enough that substantial code can be shared. Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Steve Sakoman <steve@sakoman.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
72 lines
2.3 KiB
C
72 lines
2.3 KiB
C
/*
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* (C) Copyright 2008
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* Texas Instruments, <www.ti.com>
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*
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/clocks.h>
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#include <asm/arch/sys_proto.h>
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/************************************************************
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* sdelay() - simple spin loop. Will be constant time as
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* its generally used in bypass conditions only. This
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* is necessary until timers are accessible.
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*
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* not inline to increase chances its in cache when called
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*************************************************************/
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void sdelay(unsigned long loops)
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{
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__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
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"bne 1b":"=r" (loops):"0"(loops));
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}
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/*****************************************************************
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* sr32 - clear & set a value in a bit range for a 32 bit address
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*****************************************************************/
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void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value)
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{
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u32 tmp, msk = 0;
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msk = 1 << num_bits;
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--msk;
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tmp = readl((u32)addr) & ~(msk << start_bit);
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tmp |= value << start_bit;
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writel(tmp, (u32)addr);
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}
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/*********************************************************************
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* wait_on_value() - common routine to allow waiting for changes in
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* volatile regs.
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*********************************************************************/
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u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
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u32 bound)
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{
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u32 i = 0, val;
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do {
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++i;
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val = readl((u32)read_addr) & read_bit_mask;
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if (val == match_value)
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return 1;
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if (i == bound)
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return 0;
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} while (1);
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}
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