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c61897bf02
Currently, the I2C clocks are configured in the sunxi board code. Add the I2C clocks to the DM clock driver so they can be enabled from the DM I2C driver using the normal uclass methods. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
114 lines
3.6 KiB
C
114 lines
3.6 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2018 Amarula Solutions B.V.
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <clk/sunxi.h>
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#include <dt-bindings/clock/sun6i-a31-ccu.h>
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#include <dt-bindings/reset/sun6i-a31-ccu.h>
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#include <linux/bitops.h>
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static struct ccu_clk_gate a31_gates[] = {
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[CLK_AHB1_MMC0] = GATE(0x060, BIT(8)),
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[CLK_AHB1_MMC1] = GATE(0x060, BIT(9)),
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[CLK_AHB1_MMC2] = GATE(0x060, BIT(10)),
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[CLK_AHB1_MMC3] = GATE(0x060, BIT(11)),
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[CLK_AHB1_EMAC] = GATE(0x060, BIT(17)),
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[CLK_AHB1_SPI0] = GATE(0x060, BIT(20)),
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[CLK_AHB1_SPI1] = GATE(0x060, BIT(21)),
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[CLK_AHB1_SPI2] = GATE(0x060, BIT(22)),
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[CLK_AHB1_SPI3] = GATE(0x060, BIT(23)),
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[CLK_AHB1_OTG] = GATE(0x060, BIT(24)),
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[CLK_AHB1_EHCI0] = GATE(0x060, BIT(26)),
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[CLK_AHB1_EHCI1] = GATE(0x060, BIT(27)),
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[CLK_AHB1_OHCI0] = GATE(0x060, BIT(29)),
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[CLK_AHB1_OHCI1] = GATE(0x060, BIT(30)),
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[CLK_AHB1_OHCI2] = GATE(0x060, BIT(31)),
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[CLK_APB2_I2C0] = GATE(0x06c, BIT(0)),
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[CLK_APB2_I2C1] = GATE(0x06c, BIT(1)),
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[CLK_APB2_I2C2] = GATE(0x06c, BIT(2)),
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[CLK_APB2_I2C3] = GATE(0x06c, BIT(3)),
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[CLK_APB2_UART0] = GATE(0x06c, BIT(16)),
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[CLK_APB2_UART1] = GATE(0x06c, BIT(17)),
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[CLK_APB2_UART2] = GATE(0x06c, BIT(18)),
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[CLK_APB2_UART3] = GATE(0x06c, BIT(19)),
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[CLK_APB2_UART4] = GATE(0x06c, BIT(20)),
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[CLK_APB2_UART5] = GATE(0x06c, BIT(21)),
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[CLK_SPI0] = GATE(0x0a0, BIT(31)),
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[CLK_SPI1] = GATE(0x0a4, BIT(31)),
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[CLK_SPI2] = GATE(0x0a8, BIT(31)),
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[CLK_SPI3] = GATE(0x0ac, BIT(31)),
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[CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
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[CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
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[CLK_USB_PHY2] = GATE(0x0cc, BIT(10)),
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[CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
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[CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
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[CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)),
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};
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static struct ccu_reset a31_resets[] = {
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[RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
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[RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
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[RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
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[RST_AHB1_MMC0] = RESET(0x2c0, BIT(8)),
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[RST_AHB1_MMC1] = RESET(0x2c0, BIT(9)),
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[RST_AHB1_MMC2] = RESET(0x2c0, BIT(10)),
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[RST_AHB1_MMC3] = RESET(0x2c0, BIT(11)),
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[RST_AHB1_EMAC] = RESET(0x2c0, BIT(17)),
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[RST_AHB1_SPI0] = RESET(0x2c0, BIT(20)),
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[RST_AHB1_SPI1] = RESET(0x2c0, BIT(21)),
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[RST_AHB1_SPI2] = RESET(0x2c0, BIT(22)),
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[RST_AHB1_SPI3] = RESET(0x2c0, BIT(23)),
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[RST_AHB1_OTG] = RESET(0x2c0, BIT(24)),
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[RST_AHB1_EHCI0] = RESET(0x2c0, BIT(26)),
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[RST_AHB1_EHCI1] = RESET(0x2c0, BIT(27)),
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[RST_AHB1_OHCI0] = RESET(0x2c0, BIT(29)),
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[RST_AHB1_OHCI1] = RESET(0x2c0, BIT(30)),
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[RST_AHB1_OHCI2] = RESET(0x2c0, BIT(31)),
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[RST_APB2_I2C0] = RESET(0x2d8, BIT(0)),
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[RST_APB2_I2C1] = RESET(0x2d8, BIT(1)),
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[RST_APB2_I2C2] = RESET(0x2d8, BIT(2)),
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[RST_APB2_I2C3] = RESET(0x2d8, BIT(3)),
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[RST_APB2_UART0] = RESET(0x2d8, BIT(16)),
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[RST_APB2_UART1] = RESET(0x2d8, BIT(17)),
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[RST_APB2_UART2] = RESET(0x2d8, BIT(18)),
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[RST_APB2_UART3] = RESET(0x2d8, BIT(19)),
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[RST_APB2_UART4] = RESET(0x2d8, BIT(20)),
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[RST_APB2_UART5] = RESET(0x2d8, BIT(21)),
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};
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static const struct ccu_desc a31_ccu_desc = {
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.gates = a31_gates,
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.resets = a31_resets,
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};
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static int a31_clk_bind(struct udevice *dev)
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{
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return sunxi_reset_bind(dev, ARRAY_SIZE(a31_resets));
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}
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static const struct udevice_id a31_clk_ids[] = {
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{ .compatible = "allwinner,sun6i-a31-ccu",
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.data = (ulong)&a31_ccu_desc },
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{ }
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};
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U_BOOT_DRIVER(clk_sun6i_a31) = {
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.name = "sun6i_a31_ccu",
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.id = UCLASS_CLK,
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.of_match = a31_clk_ids,
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.priv_auto = sizeof(struct ccu_priv),
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.ops = &sunxi_clk_ops,
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.probe = sunxi_clk_probe,
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.bind = a31_clk_bind,
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};
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