Fabio Estevam 782b028841 mx5: lowlevel_init.S: Fix PLL settings for mx53 ... Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz. Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 400MHz instead. Without doing so, it is not possible to use a 2.6.35 FSL kernel and display HDMI at 1080p because the IPU clock cannot reach the requested frequency. Set PLL2 to 400MHz, so that 1080p can be played and the DDR2 can run at its maximum frequency. Also, setup the other PLL's as done in FSL U-boot and re-arrange the code a little bit to allow easier comparison with the original clock setup from FSL U-boot. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>		2012-10-17 18:09:34 +02:00
..
clock.h	mx5/6 clocks: Fix SDHC clocks	2012-10-15 11:54:12 -07:00
crm_regs.h	mx5 clocks: Fix get_lp_apm()	2012-10-15 11:54:11 -07:00
gpio.h	MX: Set a common gpio.h for all i.MX	2012-09-01 14:58:27 +02:00
imx-regs.h	mx5: lowlevel_init.S: Fix PLL settings for mx53	2012-10-17 18:09:34 +02:00
iomux-mx51.h	mx5: add iomux-mx51.h include	2012-09-01 14:58:29 +02:00
iomux.h	MX5: PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH exchanged	2012-05-15 08:31:35 +02:00
mx5x_pins.h	imx: Remove unneeded/repititive definitions from imx headers	2012-04-16 14:53:59 +02:00
sys_proto.h	mx53loco: Allow to print CPU information at a later stage	2012-05-15 08:31:32 +02:00