mirror of
https://github.com/AsahiLinux/u-boot
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2d9c33ca3f
As driver model takes care of pin control configuraion, this patch also removes the sdram/fmc pin configuration. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
146 lines
2.5 KiB
C
146 lines
2.5 KiB
C
/*
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* (C) Copyright 2016
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* Vikas Manocha, <vikas.manocha@st.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <ram.h>
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#include <asm/io.h>
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#include <asm/armv7m.h>
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#include <asm/arch/stm32.h>
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#include <asm/arch/gpio.h>
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#include <dm/platdata.h>
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#include <dm/platform_data/serial_stm32x7.h>
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#include <asm/arch/stm32_periph.h>
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#include <asm/arch/stm32_defs.h>
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#include <asm/arch/syscfg.h>
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DECLARE_GLOBAL_DATA_PTR;
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const struct stm32_gpio_ctl gpio_ctl_gpout = {
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.mode = STM32_GPIO_MODE_OUT,
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.otype = STM32_GPIO_OTYPE_PP,
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.speed = STM32_GPIO_SPEED_50M,
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.pupd = STM32_GPIO_PUPD_NO,
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.af = STM32_GPIO_AF0
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};
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static int fmc_setup_gpio(void)
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{
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clock_setup(GPIO_B_CLOCK_CFG);
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clock_setup(GPIO_C_CLOCK_CFG);
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clock_setup(GPIO_D_CLOCK_CFG);
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clock_setup(GPIO_E_CLOCK_CFG);
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clock_setup(GPIO_F_CLOCK_CFG);
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clock_setup(GPIO_G_CLOCK_CFG);
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clock_setup(GPIO_H_CLOCK_CFG);
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return 0;
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}
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int dram_init(void)
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{
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struct udevice *dev;
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struct ram_info ram;
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int rv;
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rv = fmc_setup_gpio();
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if (rv)
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return rv;
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clock_setup(FMC_CLOCK_CFG);
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rv = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (rv) {
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debug("DRAM init failed: %d\n", rv);
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return rv;
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}
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rv = ram_get_info(dev, &ram);
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if (rv) {
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debug("Cannot get DRAM size: %d\n", rv);
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return rv;
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}
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debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size);
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gd->ram_size = ram.size;
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/*
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* Fill in global info with description of SRAM configuration
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*/
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gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
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gd->bd->bi_dram[0].size = ram.size;
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return rv;
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}
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int uart_setup_gpio(void)
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{
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clock_setup(GPIO_A_CLOCK_CFG);
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clock_setup(GPIO_B_CLOCK_CFG);
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return 0;
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}
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#ifdef CONFIG_ETH_DESIGNWARE
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static int stmmac_setup(void)
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{
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clock_setup(SYSCFG_CLOCK_CFG);
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/* Set >RMII mode */
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STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
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clock_setup(GPIO_A_CLOCK_CFG);
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clock_setup(GPIO_C_CLOCK_CFG);
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clock_setup(GPIO_G_CLOCK_CFG);
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clock_setup(STMMAC_CLOCK_CFG);
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return 0;
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}
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#endif
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#ifdef CONFIG_STM32_QSPI
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static int qspi_setup(void)
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{
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clock_setup(GPIO_B_CLOCK_CFG);
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clock_setup(GPIO_D_CLOCK_CFG);
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clock_setup(GPIO_E_CLOCK_CFG);
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return 0;
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}
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#endif
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u32 get_board_rev(void)
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{
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return 0;
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}
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int board_early_init_f(void)
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{
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int res;
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res = uart_setup_gpio();
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if (res)
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return res;
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#ifdef CONFIG_ETH_DESIGNWARE
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res = stmmac_setup();
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if (res)
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return res;
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#endif
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#ifdef CONFIG_STM32_QSPI
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res = qspi_setup();
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if (res)
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return res;
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#endif
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return 0;
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}
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int board_init(void)
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{
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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