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Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link Initialization says that TXDCLK_2X_SEL bit needs to be enabled for PCIe Root Complex mode. Same change was included in TF-A project: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9408 Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
264 lines
7.2 KiB
C
264 lines
7.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2015-2016 Marvell International Ltd.
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*/
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#ifndef _COMPHY_A3700_H_
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#define _COMPHY_A3700_H_
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#include "comphy_core.h"
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#define MVEBU_REG(offs) \
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((void __iomem *)(ulong)MVEBU_REGISTER(offs))
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#define DEFAULT_REFCLK_MHZ 25
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#define PLL_SET_DELAY_US 600
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#define PLL_LOCK_TIMEOUT 1000
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#define POLL_16B_REG 1
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#define POLL_32B_REG 0
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/*
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* COMPHY SB definitions
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*/
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#define COMPHY_SEL_ADDR MVEBU_REG(0x0183FC)
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#define COMPHY_PHY_CFG1_ADDR(lane) MVEBU_REG(0x018300 + (1 - lane) * 0x28)
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#define rb_pin_pu_iveref BIT(1)
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#define rb_pin_reset_core BIT(11)
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#define rb_pin_reset_comphy BIT(12)
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#define rb_pin_pu_pll BIT(16)
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#define rb_pin_pu_rx BIT(17)
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#define rb_pin_pu_tx BIT(18)
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#define rb_pin_tx_idle BIT(19)
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#define rf_gen_rx_sel_shift 22
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#define rf_gen_rx_select (0x0F << rf_gen_rx_sel_shift)
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#define rf_gen_tx_sel_shift 26
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#define rf_gen_tx_select (0x0F << rf_gen_tx_sel_shift)
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#define rb_phy_rx_init BIT(30)
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#define COMPHY_PHY_STAT1_ADDR(lane) MVEBU_REG(0x018318 + (1 - lane) * 0x28)
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#define rb_rx_init_done BIT(0)
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#define rb_pll_ready_rx BIT(2)
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#define rb_pll_ready_tx BIT(3)
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/*
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* PCIe/USB/SGMII definitions
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*/
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#define PCIE_BASE MVEBU_REG(0x070000)
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#define PCIETOP_BASE MVEBU_REG(0x080000)
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#define PCIE_RAMBASE MVEBU_REG(0x08C000)
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#define PCIEPHY_BASE MVEBU_REG(0x01F000)
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#define PCIEPHY_SHFT 2
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#define USB32_BASE MVEBU_REG(0x050000) /* usb3 device */
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#define USB32H_BASE MVEBU_REG(0x058000) /* usb3 host */
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#define USB3PHY_BASE MVEBU_REG(0x05C000)
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#define USB2PHY_BASE MVEBU_REG(0x05D000)
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#define USB2PHY2_BASE MVEBU_REG(0x05F000)
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#define USB32_CTRL_BASE MVEBU_REG(0x05D800)
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#define USB3PHY_SHFT 2
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#define USB3PHY_LANE2_REG_BASE_OFFSET 0x200
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static inline void __iomem *sgmiiphy_addr(u32 lane, u32 addr)
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{
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addr = (addr & 0x00007FF) * 2;
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if (lane == 1)
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return PCIEPHY_BASE + addr;
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else
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return USB3PHY_BASE + addr;
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}
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/* units */
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enum phy_unit {
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PCIE = 1,
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USB3 = 2,
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};
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static inline void __iomem *phy_addr(enum phy_unit unit, u32 addr)
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{
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if (unit == PCIE)
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return PCIEPHY_BASE + addr * PCIEPHY_SHFT;
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else
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return USB3PHY_BASE + addr * USB3PHY_SHFT;
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}
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/* bit definition for USB32_CTRL_BASE (USB32 Control Mode) */
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#define usb32_ctrl_id_mode BIT(0)
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#define usb32_ctrl_soft_id BIT(1)
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#define usb32_ctrl_int_mode BIT(4)
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#define PWR_PLL_CTRL 0x01
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#define rf_phy_mode_shift 5
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#define rf_phy_mode_mask (0x7 << rf_phy_mode_shift)
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#define rf_ref_freq_sel_shift 0
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#define rf_ref_freq_sel_mask (0x1F << rf_ref_freq_sel_shift)
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#define PHY_MODE_SGMII 0x4
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#define KVCO_CAL_CTRL 0x02
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#define rb_use_max_pll_rate BIT(12)
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#define rb_force_calibration_done BIT(9)
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#define DIG_LB_EN 0x23
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#define rf_data_width_shift 10
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#define rf_data_width_mask (0x3 << rf_data_width_shift)
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#define SYNC_PATTERN 0x24
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#define phy_txd_inv BIT(10)
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#define phy_rxd_inv BIT(11)
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#define SYNC_MASK_GEN 0x25
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#define rb_idle_sync_en BIT(12)
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#define UNIT_CTRL 0x48
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#define GEN2_SETTINGS_2 0x3e
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#define g2_tx_ssc_amp BIT(14)
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#define GEN2_SETTINGS_3 0x3f
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#define GEN3_SETTINGS_3 0x112
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#define MISC_REG0 0x4f
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#define rb_clk100m_125m_en BIT(4)
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#define rb_txdclk_2x_sel BIT(6)
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#define rb_clk500m_en BIT(7)
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#define rb_ref_clk_sel BIT(10)
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#define UNIT_IFACE_REF_CLK_CTRL 0x51
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#define rb_ref1m_gen_div_force BIT(8)
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#define rf_ref1m_gen_div_value_shift 0
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#define rf_ref1m_gen_div_value_mask (0xFF << rf_ref1m_gen_div_value_shift)
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#define UNIT_ERR_CNT_CONST_CTRL 0x6a
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#define rb_fast_dfe_enable BIT(13)
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#define MISC_REG1 0x73
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#define bf_sel_bits_pcie_force BIT(15)
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#define LANE_CFG0 0x180
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#define bf_use_max_pll_rate BIT(9)
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#define LANE_CFG1 0x181
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#define bf_use_max_pll_rate BIT(9)
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#define prd_txdeemph1_mask BIT(15)
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#define tx_det_rx_mode BIT(6)
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#define gen2_tx_data_dly_deft (2 << 3)
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#define gen2_tx_data_dly_mask (BIT(3) | BIT(4))
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#define tx_elec_idle_mode_en BIT(0)
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#define LANE_CFG4 0x188
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#define bf_spread_spectrum_clock_en BIT(7)
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#define LANE_STAT1 0x183
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#define rb_txdclk_pclk_en BIT(0)
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#define GLOB_PHY_CTRL0 0x1c1
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#define bf_soft_rst BIT(0)
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#define bf_mode_refdiv 0x30
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#define rb_mode_core_clk_freq_sel BIT(9)
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#define rb_mode_pipe_width_32 BIT(3)
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#define TEST_MODE_CTRL 0x1c2
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#define rb_mode_margin_override BIT(2)
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#define GLOB_CLK_SRC_LO 0x1c3
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#define bf_cfg_sel_20b BIT(15)
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#define PWR_MGM_TIM1 0x1d0
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#define PCIE_REF_CLK_ADDR (PCIE_BASE + 0x4814)
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#define USB3_CTRPUL_VAL_REG (0x20 + USB32_BASE)
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#define USB3H_CTRPUL_VAL_REG (0x3454 + USB32H_BASE)
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#define rb_usb3_ctr_100ns 0xff000000
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#define USB2_OTG_PHY_CTRL_ADDR (0x820 + USB2PHY_BASE)
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#define rb_usb2phy_suspm BIT(14)
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#define rb_usb2phy_pu BIT(0)
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#define USB2_PHY_OTG_CTRL_ADDR (0x34 + USB2PHY_BASE)
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#define rb_pu_otg BIT(4)
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#define USB2_PHY_CHRGR_DET_ADDR (0x38 + USB2PHY_BASE)
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#define rb_cdp_en BIT(2)
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#define rb_dcp_en BIT(3)
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#define rb_pd_en BIT(4)
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#define rb_pu_chrg_dtc BIT(5)
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#define rb_cdp_dm_auto BIT(7)
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#define rb_enswitch_dp BIT(12)
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#define rb_enswitch_dm BIT(13)
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#define USB2_CAL_CTRL_ADDR (0x8 + USB2PHY_BASE)
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#define rb_usb2phy_pllcal_done BIT(31)
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#define rb_usb2phy_impcal_done BIT(23)
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#define USB2_PLL_CTRL0_ADDR (0x0 + USB2PHY_BASE)
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#define rb_usb2phy_pll_ready BIT(31)
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#define USB2_RX_CHAN_CTRL1_ADDR (0x18 + USB2PHY_BASE)
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#define rb_usb2phy_sqcal_done BIT(31)
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#define USB2_PHY2_CTRL_ADDR (0x804 + USB2PHY2_BASE)
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#define rb_usb2phy2_suspm BIT(7)
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#define rb_usb2phy2_pu BIT(0)
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#define USB2_PHY2_CAL_CTRL_ADDR (0x8 + USB2PHY2_BASE)
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#define USB2_PHY2_PLL_CTRL0_ADDR (0x0 + USB2PHY2_BASE)
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#define USB2_PHY2_RX_CHAN_CTRL1_ADDR (0x18 + USB2PHY2_BASE)
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#define USB2_PHY_BASE(usb32) (usb32 == 0 ? USB2PHY2_BASE : USB2PHY_BASE)
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#define USB2_PHY_CTRL_ADDR(usb32) \
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(usb32 == 0 ? USB2_PHY2_CTRL_ADDR : USB2_OTG_PHY_CTRL_ADDR)
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#define RB_USB2PHY_SUSPM(usb32) \
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(usb32 == 0 ? rb_usb2phy2_suspm : rb_usb2phy_suspm)
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#define RB_USB2PHY_PU(usb32) \
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(usb32 == 0 ? rb_usb2phy2_pu : rb_usb2phy_pu)
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#define USB2_PHY_CAL_CTRL_ADDR(usb32) \
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(usb32 == 0 ? USB2_PHY2_CAL_CTRL_ADDR : USB2_CAL_CTRL_ADDR)
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#define USB2_PHY_RX_CHAN_CTRL1_ADDR(usb32) \
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(usb32 == 0 ? USB2_PHY2_RX_CHAN_CTRL1_ADDR : USB2_RX_CHAN_CTRL1_ADDR)
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#define USB2_PHY_PLL_CTRL0_ADDR(usb32) \
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(usb32 == 0 ? USB2_PHY2_PLL_CTRL0_ADDR : USB2_PLL_CTRL0_ADDR)
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/*
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* SATA definitions
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*/
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#define AHCI_BASE MVEBU_REG(0xE0000)
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#define rh_vsreg_addr (AHCI_BASE + 0x178)
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#define rh_vsreg_data (AHCI_BASE + 0x17C)
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#define rh_vs0_a (AHCI_BASE + 0xA0)
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#define rh_vs0_d (AHCI_BASE + 0xA4)
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#define vphy_sync_pattern_reg 0x224
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#define bs_txd_inv BIT(10)
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#define bs_rxd_inv BIT(11)
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#define vphy_loopback_reg0 0x223
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#define bs_phyintf_40bit 0x0C00
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#define bs_pll_ready_tx 0x10
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#define vphy_power_reg0 0x201
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#define vphy_calctl_reg 0x202
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#define bs_max_pll_rate BIT(12)
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#define vphy_reserve_reg 0x0e
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#define bs_phyctrl_frm_pin BIT(13)
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#define vsata_ctrl_reg 0x00
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#define bs_phy_pu_pll BIT(6)
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/*
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* SDIO/eMMC definitions
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*/
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#define SDIO_BASE MVEBU_REG(0xD8000)
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#define SDIO_HOST_CTRL1_ADDR (SDIO_BASE + 0x28)
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#define SDIO_SDHC_FIFO_ADDR (SDIO_BASE + 0x12C)
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#define SDIO_CAP_12_ADDR (SDIO_BASE + 0x40)
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#define SDIO_ENDIAN_ADDR (SDIO_BASE + 0x1A4)
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#define SDIO_PHY_TIMING_ADDR (SDIO_BASE + 0x170)
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#define SDIO_PHY_PAD_CTRL0_ADDR (SDIO_BASE + 0x178)
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#define SDIO_DLL_RST_ADDR (SDIO_BASE + 0x148)
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#endif /* _COMPHY_A3700_H_ */
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