mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 10:48:51 +00:00
2f6a7e8ce5
USB ULPI PHY reset signals are typically active low. Consequently, they should be marked as GPIO_ACTIVE_LOW in device tree, and indeed they are in the Linux kernel DTs, and in DT properties that U-Boot doesn't yet use. However, in DT properties that U-Boot does use, the value has been set to 0 (== GPIO_ACTIVE_HIGH) to work around a bug in U-Boot. This change fixes the DT to correctly represent the HW, and fixes the Tegra USB driver to cope with the fact that dm_gpio_set_value() internally handles any inversions implied by the DT value GPIO_ACTIVE_LOW. Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
129 lines
2.4 KiB
Text
129 lines
2.4 KiB
Text
/dts-v1/;
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#include "tegra20.dtsi"
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/ {
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model = "Toradex Colibri T20";
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compatible = "toradex,colibri_t20", "nvidia,tegra20";
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chosen {
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stdout-path = &uarta;
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};
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aliases {
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i2c0 = "/i2c@7000d000";
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i2c1 = "/i2c@7000c000";
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i2c2 = "/i2c@7000c400";
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usb0 = "/usb@c5008000";
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usb1 = "/usb@c5000000";
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usb2 = "/usb@c5004000";
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mmc0 = "/sdhci@c8000600";
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};
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host1x@50000000 {
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status = "okay";
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dc@54200000 {
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status = "okay";
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rgb {
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status = "okay";
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nvidia,panel = <&lcd_panel>;
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};
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};
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};
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usb@c5000000 {
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statuc = "okay";
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dr_mode = "otg";
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};
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usb@c5004000 {
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statuc = "okay";
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/* VBUS_LAN */
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nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
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GPIO_ACTIVE_LOW>;
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nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
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};
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usb@c5008000 {
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statuc = "okay";
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/* USBH_PEN */
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nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
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};
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nand-controller@70008000 {
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nvidia,wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
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nvidia,width = <8>;
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nvidia,timing = <15 100 25 80 25 10 15 10 100>;
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nand@0 {
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reg = <0>;
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compatible = "nand-flash";
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};
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};
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/*
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* GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
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* board)
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*/
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i2c@7000c000 {
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status = "okay";
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clock-frequency = <100000>;
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};
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/* GEN2_I2C: unused */
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/* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */
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i2c@7000c400 {
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status = "okay";
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clock-frequency = <100000>;
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};
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/*
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* PWR_I2C: power I2C to PMIC and temperature sensor
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*/
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i2c@7000d000 {
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status = "okay";
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clock-frequency = <100000>;
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};
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sdhci@c8000600 {
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status = "okay";
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bus-width = <4>;
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cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
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};
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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clk32k_in: clock@0 {
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compatible = "fixed-clock";
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reg=<0>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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pwm: pwm@7000a000 {
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status = "okay";
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};
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lcd_panel: panel {
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clock = <25175000>;
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xres = <640>;
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yres = <480>;
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left-margin = <48>; /* horizontal back porch */
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right-margin = <16>; /* horizontal front porch */
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hsync-len = <96>;
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lower-margin = <11>; /* vertical front porch */
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upper-margin = <31>; /* vertical back porch */
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vsync-len = <2>;
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hsync-active-high;
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vsync-active-high;
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nvidia,bits-per-pixel = <16>;
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nvidia,pwm = <&pwm 0 0>;
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nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>;
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nvidia,panel-timings = <0 0 0 0>;
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};
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};
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