mirror of
https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
134 lines
4 KiB
C
134 lines
4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2002
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
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*/
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#ifndef _SPARTAN3_H_
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#define _SPARTAN3_H_
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#include <xilinx.h>
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/* Slave Parallel Implementation function table */
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typedef struct {
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xilinx_pre_fn pre;
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xilinx_pgm_fn pgm;
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xilinx_init_fn init;
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xilinx_err_fn err;
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xilinx_done_fn done;
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xilinx_clk_fn clk;
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xilinx_cs_fn cs;
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xilinx_wr_fn wr;
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xilinx_rdata_fn rdata;
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xilinx_wdata_fn wdata;
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xilinx_busy_fn busy;
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xilinx_abort_fn abort;
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xilinx_post_fn post;
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} xilinx_spartan3_slave_parallel_fns;
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/* Slave Serial Implementation function table */
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typedef struct {
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xilinx_pre_fn pre;
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xilinx_pgm_fn pgm;
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xilinx_clk_fn clk;
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xilinx_init_fn init;
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xilinx_done_fn done;
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xilinx_wr_fn wr;
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xilinx_post_fn post;
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xilinx_bwr_fn bwr; /* block write function */
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xilinx_abort_fn abort;
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} xilinx_spartan3_slave_serial_fns;
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#if defined(CONFIG_FPGA_SPARTAN3)
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extern struct xilinx_fpga_op spartan3_op;
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# define FPGA_SPARTAN3_OPS &spartan3_op
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#else
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# define FPGA_SPARTAN3_OPS NULL
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#endif
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/* Device Image Sizes
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*********************************************************************/
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/* Spartan-III (1.2V) */
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#define XILINX_XC3S50_SIZE 439264/8
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#define XILINX_XC3S200_SIZE 1047616/8
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#define XILINX_XC3S400_SIZE 1699136/8
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#define XILINX_XC3S1000_SIZE 3223488/8
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#define XILINX_XC3S1500_SIZE 5214784/8
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#define XILINX_XC3S2000_SIZE 7673024/8
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#define XILINX_XC3S4000_SIZE 11316864/8
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#define XILINX_XC3S5000_SIZE 13271936/8
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/* Spartan-3E (v3.4) */
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#define XILINX_XC3S100E_SIZE 581344/8
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#define XILINX_XC3S250E_SIZE 1353728/8
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#define XILINX_XC3S500E_SIZE 2270208/8
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#define XILINX_XC3S1200E_SIZE 3841184/8
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#define XILINX_XC3S1600E_SIZE 5969696/8
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/*
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* Spartan-6 : the Spartan-6 family can be programmed
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* exactly as the Spartan-3
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*/
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#define XILINK_XC6SLX4_SIZE (3713568/8)
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/* Descriptor Macros
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*********************************************************************/
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/* Spartan-III devices */
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#define XILINX_XC3S50_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, \
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FPGA_SPARTAN3_OPS }
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#define XILINX_XC3S200_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, \
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FPGA_SPARTAN3_OPS }
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#define XILINX_XC3S400_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, \
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FPGA_SPARTAN3_OPS }
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#define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, \
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FPGA_SPARTAN3_OPS }
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#define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, \
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FPGA_SPARTAN3_OPS }
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#define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, \
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FPGA_SPARTAN3_OPS }
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#define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, \
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FPGA_SPARTAN3_OPS }
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#define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, \
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FPGA_SPARTAN3_OPS }
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/* Spartan-3E devices */
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#define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, \
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FPGA_SPARTAN3_OPS }
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#define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, \
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FPGA_SPARTAN3_OPS }
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#define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, \
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FPGA_SPARTAN3_OPS }
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#define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie, \
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FPGA_SPARTAN3_OPS }
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#define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie, \
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FPGA_SPARTAN3_OPS }
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#define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \
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{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, \
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FPGA_SPARTAN3_OPS }
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#endif /* _SPARTAN3_H_ */
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