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552a848e4f
Change is consistent with other SOCs and it is in preparation for adding SOMs. SOC's related files are moved from cpu/ to mach-imx/<SOC>. This change is also coherent with the structure in kernel. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@nxp.com> CC: Akshay Bhat <akshaybhat@timesys.com> CC: Ken Lin <Ken.Lin@advantech.com.tw> CC: Marek Vasut <marek.vasut@gmail.com> CC: Heiko Schocher <hs@denx.de> CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com> CC: Christian Gmeiner <christian.gmeiner@gmail.com> CC: Stefan Roese <sr@denx.de> CC: Patrick Bruenn <p.bruenn@beckhoff.com> CC: Troy Kisky <troy.kisky@boundarydevices.com> CC: Nikita Kiryanov <nikita@compulab.co.il> CC: Otavio Salvador <otavio@ossystems.com.br> CC: "Eric Bénard" <eric@eukrea.com> CC: Jagan Teki <jagan@amarulasolutions.com> CC: Ye Li <ye.li@nxp.com> CC: Peng Fan <peng.fan@nxp.com> CC: Adrian Alonso <adrian.alonso@nxp.com> CC: Alison Wang <b18965@freescale.com> CC: Tim Harvey <tharvey@gateworks.com> CC: Martin Donnelly <martin.donnelly@ge.com> CC: Marcin Niestroj <m.niestroj@grinn-global.com> CC: Lukasz Majewski <lukma@denx.de> CC: Adam Ford <aford173@gmail.com> CC: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr> CC: Boris Brezillon <boris.brezillon@free-electrons.com> CC: Soeren Moch <smoch@web.de> CC: Richard Hu <richard.hu@technexion.com> CC: Wig Cheng <wig.cheng@technexion.com> CC: Vanessa Maegima <vanessa.maegima@nxp.com> CC: Max Krummenacher <max.krummenacher@toradex.com> CC: Stefan Agner <stefan.agner@toradex.com> CC: Markus Niebel <Markus.Niebel@tq-group.com> CC: Breno Lima <breno.lima@nxp.com> CC: Francesco Montefoschi <francesco.montefoschi@udoo.org> CC: Jaehoon Chung <jh80.chung@samsung.com> CC: Scott Wood <oss@buserror.net> CC: Joe Hershberger <joe.hershberger@ni.com> CC: Anatolij Gustschin <agust@denx.de> CC: Simon Glass <sjg@chromium.org> CC: "Andrew F. Davis" <afd@ti.com> CC: "Łukasz Majewski" <l.majewski@samsung.com> CC: Patrice Chotard <patrice.chotard@st.com> CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Hans de Goede <hdegoede@redhat.com> CC: Masahiro Yamada <yamada.masahiro@socionext.com> CC: Stephen Warren <swarren@nvidia.com> CC: Andre Przywara <andre.przywara@arm.com> CC: "Álvaro Fernández Rojas" <noltari@gmail.com> CC: York Sun <york.sun@nxp.com> CC: Xiaoliang Yang <xiaoliang.yang@nxp.com> CC: Chen-Yu Tsai <wens@csie.org> CC: George McCollister <george.mccollister@gmail.com> CC: Sven Ebenfeld <sven.ebenfeld@gmail.com> CC: Filip Brozovic <fbrozovic@gmail.com> CC: Petr Kulhavy <brain@jikos.cz> CC: Eric Nelson <eric@nelint.com> CC: Bai Ping <ping.bai@nxp.com> CC: Anson Huang <Anson.Huang@nxp.com> CC: Sanchayan Maity <maitysanchayan@gmail.com> CC: Lokesh Vutla <lokeshvutla@ti.com> CC: Patrick Delaunay <patrick.delaunay@st.com> CC: Gary Bisson <gary.bisson@boundarydevices.com> CC: Alexander Graf <agraf@suse.de> CC: u-boot@lists.denx.de Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
100 lines
3.6 KiB
C
100 lines
3.6 KiB
C
/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __RDC_SEMA_H__
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#define __RDC_SEMA_H__
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/*
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* rdc_peri_cfg_t and rdc_ma_cft_t use the same layout.
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*
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* [ 23 22 | 21 20 | 19 18 | 17 16 ] | [ 15 - 8 ] | [ 7 - 0 ]
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* d3 d2 d1 d0 | master id | peri id
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* d[x] means domain[x], x can be [3 - 0].
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*/
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typedef u32 rdc_peri_cfg_t;
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typedef u32 rdc_ma_cfg_t;
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#define RDC_PERI_SHIFT 0
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#define RDC_PERI_MASK 0xFF
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#define RDC_DOMAIN_SHIFT_BASE 16
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#define RDC_DOMAIN_MASK 0xFF0000
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#define RDC_DOMAIN_SHIFT(x) (RDC_DOMAIN_SHIFT_BASE + ((x << 1)))
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#define RDC_DOMAIN(x) ((rdc_peri_cfg_t)(0x3 << RDC_DOMAIN_SHIFT(x)))
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#define RDC_MASTER_SHIFT 8
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#define RDC_MASTER_MASK 0xFF00
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#define RDC_MASTER_CFG(master_id, domain_id) (rdc_ma_cfg_t)((master_id << 8) | \
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(domain_id << RDC_DOMAIN_SHIFT_BASE))
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/* The Following macro definitions are common to i.MX6SX and i.MX7D */
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#define SEMA_GATES_NUM 64
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#define RDC_MDA_DID_SHIFT 0
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#define RDC_MDA_DID_MASK (0x3 << RDC_MDA_DID_SHIFT)
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#define RDC_MDA_LCK_SHIFT 31
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#define RDC_MDA_LCK_MASK (0x1 << RDC_MDA_LCK_SHIFT)
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#define RDC_PDAP_DW_SHIFT(domain) ((domain) << 1)
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#define RDC_PDAP_DR_SHIFT(domain) (1 + RDC_PDAP_DW_SHIFT(domain))
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#define RDC_PDAP_DW_MASK(domain) (1 << RDC_PDAP_DW_SHIFT(domain))
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#define RDC_PDAP_DR_MASK(domain) (1 << RDC_PDAP_DR_SHIFT(domain))
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#define RDC_PDAP_DRW_MASK(domain) (RDC_PDAP_DW_MASK(domain) | \
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RDC_PDAP_DR_MASK(domain))
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#define RDC_PDAP_SREQ_SHIFT 30
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#define RDC_PDAP_SREQ_MASK (0x1 << RDC_PDAP_SREQ_SHIFT)
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#define RDC_PDAP_LCK_SHIFT 31
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#define RDC_PDAP_LCK_MASK (0x1 << RDC_PDAP_LCK_SHIFT)
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#define RDC_MRSA_SADR_SHIFT 7
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#define RDC_MRSA_SADR_MASK (0x1ffffff << RDC_MRSA_SADR_SHIFT)
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#define RDC_MREA_EADR_SHIFT 7
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#define RDC_MREA_EADR_MASK (0x1ffffff << RDC_MREA_EADR_SHIFT)
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#define RDC_MRC_DW_SHIFT(domain) (domain)
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#define RDC_MRC_DR_SHIFT(domain) (1 + RDC_MRC_DW_SHIFT(domain))
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#define RDC_MRC_DW_MASK(domain) (1 << RDC_MRC_DW_SHIFT(domain))
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#define RDC_MRC_DR_MASK(domain) (1 << RDC_MRC_DR_SHIFT(domain))
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#define RDC_MRC_DRW_MASK(domain) (RDC_MRC_DW_MASK(domain) | \
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RDC_MRC_DR_MASK(domain))
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#define RDC_MRC_ENA_SHIFT 30
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#define RDC_MRC_ENA_MASK (0x1 << RDC_MRC_ENA_SHIFT)
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#define RDC_MRC_LCK_SHIFT 31
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#define RDC_MRC_LCK_MASK (0x1 << RDC_MRC_LCK_SHIFT)
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#define RDC_MRVS_VDID_SHIFT 0
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#define RDC_MRVS_VDID_MASK (0x3 << RDC_MRVS_VDID_SHIFT)
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#define RDC_MRVS_AD_SHIFT 4
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#define RDC_MRVS_AD_MASK (0x1 << RDC_MRVS_AD_SHIFT)
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#define RDC_MRVS_VADDR_SHIFT 5
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#define RDC_MRVS_VADDR_MASK (0x7ffffff << RDC_MRVS_VADDR_SHIFT)
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#define RDC_SEMA_GATE_GTFSM_SHIFT 0
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#define RDC_SEMA_GATE_GTFSM_MASK (0xf << RDC_SEMA_GATE_GTFSM_SHIFT)
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#define RDC_SEMA_GATE_LDOM_SHIFT 5
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#define RDC_SEMA_GATE_LDOM_MASK (0x3 << RDC_SEMA_GATE_LDOM_SHIFT)
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#define RDC_SEMA_RSTGT_RSTGDP_SHIFT 0
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#define RDC_SEMA_RSTGT_RSTGDP_MASK (0xff << RDC_SEMA_RSTGT_RSTGDP_SHIFT)
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#define RDC_SEMA_RSTGT_RSTGSM_SHIFT 2
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#define RDC_SEMA_RSTGT_RSTGSM_MASK (0x3 << RDC_SEMA_RSTGT_RSTGSM_SHIFT)
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#define RDC_SEMA_RSTGT_RSTGMS_SHIFT 4
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#define RDC_SEMA_RSTGT_RSTGMS_MASK (0xf << RDC_SEMA_RSTGT_RSTGMS_SHIFT)
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#define RDC_SEMA_RSTGT_RSTGTN_SHIFT 8
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#define RDC_SEMA_RSTGT_RSTGTN_MASK (0xff << RDC_SEMA_RSTGT_RSTGTN_SHIFT)
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int imx_rdc_check_permission(int per_id, int dom_id);
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int imx_rdc_sema_lock(int per_id);
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int imx_rdc_sema_unlock(int per_id);
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int imx_rdc_setup_peri(rdc_peri_cfg_t p);
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int imx_rdc_setup_peripherals(rdc_peri_cfg_t const *peripherals_list,
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unsigned count);
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int imx_rdc_setup_ma(rdc_ma_cfg_t p);
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int imx_rdc_setup_masters(rdc_ma_cfg_t const *masters_list, unsigned count);
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#endif /* __RDC_SEMA_H__*/
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