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Erratum NO. FE-9144572: The device SPI interface supports frequencies of up to 50 MHz. However, due to this erratum, when the device core clock is 250 MHz and the SPI interfaces is configured for 50MHz SPI clock and CPOL=CPHA=1 there might occur data corruption on reads from the SPI device. Implement the workaround by setting the TMISO_SAMPLE value to 0x2 in the timing1 register. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
72 lines
2.2 KiB
C
72 lines
2.2 KiB
C
/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* Derived from drivers/spi/mpc8xxx_spi.c
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __KW_SPI_H__
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#define __KW_SPI_H__
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/* SPI Registers on kirkwood SOC */
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struct kwspi_registers {
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u32 ctrl; /* 0x10600 */
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u32 cfg; /* 0x10604 */
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u32 dout; /* 0x10608 */
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u32 din; /* 0x1060c */
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u32 irq_cause; /* 0x10610 */
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u32 irq_mask; /* 0x10614 */
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u32 timing1; /* 0x10618 */
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u32 timing2; /* 0x1061c */
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u32 dw_cfg; /* 0x10620 - Direct Write Configuration */
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};
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/* They are used to define CONFIG_SYS_KW_SPI_MPP
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* each of the below #defines selects which mpp is
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* configured for each SPI signal in spi_claim_bus
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* bit 0: selects pin for MOSI (MPP1 if 0, MPP6 if 1)
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* bit 1: selects pin for SCK (MPP2 if 0, MPP10 if 1)
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* bit 2: selects pin for MISO (MPP3 if 0, MPP11 if 1)
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*/
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#define MOSI_MPP6 (1 << 0)
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#define SCK_MPP10 (1 << 1)
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#define MISO_MPP11 (1 << 2)
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/* Control Register */
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#define KWSPI_CSN_ACT (1 << 0) /* Activates serial memory interface */
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#define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */
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#define KWSPI_CS_SHIFT 2 /* chip select shift */
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#define KWSPI_CS_MASK 0x7 /* chip select mask */
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/* Configuration Register */
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#define KWSPI_CLKPRESCL_MASK 0x1f
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#define KWSPI_CLKPRESCL_MIN 0x12
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#define KWSPI_XFERLEN_1BYTE 0
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#define KWSPI_XFERLEN_2BYTE (1 << 5)
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#define KWSPI_XFERLEN_MASK (1 << 5)
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#define KWSPI_ADRLEN_1BYTE 0
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#define KWSPI_ADRLEN_2BYTE (1 << 8)
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#define KWSPI_ADRLEN_3BYTE (2 << 8)
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#define KWSPI_ADRLEN_4BYTE (3 << 8)
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#define KWSPI_ADRLEN_MASK (3 << 8)
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#define KWSPI_CPOL (1 << 11)
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#define KWSPI_CPHA (1 << 12)
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#define KWSPI_TXLSBF (1 << 13)
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#define KWSPI_RXLSBF (1 << 14)
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/* Timing Parameters 1 Register */
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#define KW_SPI_TMISO_SAMPLE_OFFSET 6
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#define KW_SPI_TMISO_SAMPLE_MASK (0x3 << KW_SPI_TMISO_SAMPLE_OFFSET)
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#define KW_SPI_TMISO_SAMPLE_1 (1 << KW_SPI_TMISO_SAMPLE_OFFSET)
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#define KW_SPI_TMISO_SAMPLE_2 (2 << KW_SPI_TMISO_SAMPLE_OFFSET)
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#define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */
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#define KWSPI_IRQMASK 0 /* mask SPI interrupt */
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#define KWSPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */
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#define KWSPI_TIMEOUT 10000
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#endif /* __KW_SPI_H__ */
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